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es-ude / ElasticNodeHardware

Schematics and Board design for elastic node hardware
MIT License
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LTC3569 - Datasheet states that power rail voltage drops when switching the enable pin of the LTC3569 respective power rail #4

Open LeoBuron opened 1 month ago

LeoBuron commented 1 month ago

The Output is computed with

VOUT1 = VREF1(1 + R1/R2) with R1=30k and R2=120k => VOUT1 = 1.0V VOUT2 = VREF2(1 + R3/R4) with R3=150k and R4=120k => VOUT2 = 1.8V

VREF starts at 0.8V and will decrease everytime it the respective enable pin is switched by 25mV down to 0.425V. This means that everytime we switch the FPGA power on and off, the VREF1 and VREF2 will go down by 25mV. Which will result in drops of 31.25mV for VOUT1 and 56.25mV for VOUT2. We should definitly check if the behaviour is like that. This would mean that we can not really turn off and on the FPGA multiple times.

Datasheet of the LTC2569: https://www.mouser.de/datasheet/2/609/3569fe-2954846.pdf See page 15.

SuperChange001 commented 4 weeks ago

you misread it; it says we can program the Vref by giving a square wave on the enable pin; see Figure 3 in the datasheet.

LeoBuron commented 4 weeks ago

Sure. But if we enable and disbale the ltc3569 fast, we generate a square wave. So the problem might still occur.