Closed julianhoever closed 1 year ago
@glencoe I added you to this issue because you are currently working on implementing the bufferless interface. During this we could fix the issue with different signal widths in the sequential vhd file for a model with more than one layer.
An example is that for a model consisting out of two linear layers the x_address
of the sequential (x_address: out std_logic_vector(1-1 downto 0);
) will be connected to the i_fplinear_0_x_address
of the first linear layer (signal i_fplinear_0_x_address : std_logic_vector(1 downto 0) := (others => '0');
) but they have different bit widths.
This bug causes Vivado to fail during synthesizing the two layer MLP.
During an ElasticAI.Creator tutorial, we found that Vivado throws an error when we try to synthesize a two-layer MLP that consists only of linear layers.