SPI Host of X-HEEP needs to acknowledge whenever there is an event interrupt, contrarily to Opentitan's SPI Host.
Opentitan SPI Host EVENT_ENABLE bit of INTR_STATE register is of type ro (read only), while X-HEEP's register bit is rw1c (read write 1 to clear).
Similarly to an error interrupt, if there is an event interrupt, the interrupt will fire in loop if the event is not acknowledged by writing a 1 to the EVENT_ENABLE bit in the INTR_STATE register.
SPI Host of X-HEEP needs to acknowledge whenever there is an event interrupt, contrarily to Opentitan's SPI Host.
Opentitan SPI Host
EVENT_ENABLEbit ofINTR_STATEregister is of type ro (read only), while X-HEEP's register bit is rw1c (read write 1 to clear).Similarly to an error interrupt, if there is an event interrupt, the interrupt will fire in loop if the event is not acknowledged by writing a 1 to the
EVENT_ENABLEbit in theINTR_STATEregister.