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esl-epfl / x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
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Reset active by default on Nexys A7 #593

Open davidmallasen opened 1 month ago

davidmallasen commented 1 month ago

On the Nexys A7, @luispimo realized that the jtag_trst_ni is connected to switch 0, so than reset is active by default. https://github.com/esl-epfl/x-heep/blob/2c6d7d8f581020d4961bd08dbd3956c90b676085/hw/fpga/constraints/nexys/pin_assign.xdc#L24 This can be confusing unless you read the pin assign, so we could either fix this by mapping this reset to a button (high by default) or at least by documenting this in the RunOnFPGA.

davideschiavone commented 1 day ago

We may want to invert the polarity in the wrapper so that by default is not active, or indeed assign it to a button.

Feel free to suggest and make a modification