Cache enable routine seems to be incomplete

[Josfemova]

Hello,

Some days ago me and some peers noticed that disabling lto makes irom a non-usable section for ROTEXT We tracked this behavior and found that it was caused by a change in the commit right after version 4.0: One quick solution (for those who must avoid lto for x or y reason) is to fork the repo and add back the PROVIDE ( Cache_Read_Enable = 0x40004678 ); to memory.x , plus modifying lib.rs so it calls the sdk function instead of the hal one

pub unsafe extern "C" fn ESP8266Reset() -> ! {
    // These symbols come from `memory.x`
    extern "C" {
        static mut _rtc_bss_start: u32;
        static mut _rtc_bss_end: u32;
        pub fn Cache_Read_Enable(odd_even:u8, mb_count:u8, no_idea:u8);
    }
    // configure the pll for the most common crystal frequency
    ...

    //use just one
    Cache_Read_Enable(0, 0, 0); //sdk version works regardless of lto config
    flash::cache_enable(&mut dp.SPI0, 0); //does the same as Cache_Read_Enable but not quite
    ...
}

the hal implementation of cache_enable seems to follow the behavior found here, and it does work, but not quite. I am still unable to find what lto changes that makes this implementation work with lto enabled, but not with lto disabled. Disabling lto causes undefined behavior, script wont run and if you open a serial monitor all you'll see is noise.

Idk if the sdk method should be added back into the main repo while this is troubleshooted, but I did want to leave this documented in case it is helpful for someone in a similar situation (similar situation being: lto MUST be disabled for your stuff to work)

[icewind1991]

should be fixed now.

The issue was not in the cache_enable implementation but svd2rust not adding #[inline] is all the required places, meaning that without lto it was trying to jump into flash memory while it was trying to setup the mapping.