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esp-rs / espflash

Serial flasher utility for Espressif SoCs and modules based on esptool.py
Apache License 2.0
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QIO flash-mode does not work (at least with esp-s3-wroom-1-N16R8) #657

Open liebman opened 1 month ago

liebman commented 1 month ago

If you specify the flash mode or qio to espflash then it fails to boot:

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x2b (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:QIO, clock div:1
load:0x3fce3818,len:0x16f8
ets_loader.c 78 
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x7 (TG0WDT_SYS_RST),boot:0x2b (SPI_FAST_FLASH_BOOT)
Saved PC:0x400454d5
SPIWP:0xee
mode:QIO, clock div:1
load:0x3fce3818,len:0x16f8
ets_loader.c 78

However If I build and copy a bootloader.bin from an esp-idf project that specifies the QIO flash mode and just let espflash flash as DIO it works. And the esp-idf bootloader switches to QIO.

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x2b (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3818,len:0x186c
load:0x403c9700,len:0x4
load:0x403c9704,len:0xda4
load:0x403cc700,len:0x3130
entry 0x403c9934
I (27) boot: ESP-IDF 5.1.1 2nd stage bootloader
I (27) boot: compile time Jul 27 2024 13:15:35
I (27) boot: Multicore bootloader
I (30) boot: chip revision: v0.2
I (34) qio_mode: Enabling default flash chip QIO
I (39) boot.esp32s3: Boot SPI Speed : 80MHz
I (44) boot.esp32s3: SPI Mode       : QIO
I (49) boot.esp32s3: SPI Flash Size : 16MB
I (53) boot: Enabling RNG early entropy source...
I (59) boot: Partition Table:
I (62) boot: ## Label            Usage          Type ST Offset   Length
I (70) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (77) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (85) boot:  2 app0             OTA app          00 10 00010000 003c0000
I (92) boot:  3 app1             OTA app          00 11 003d0000 003c0000
I (100) boot:  4 littlefs         Unknown data     01 82 00790000 0004e000
I (107) boot: End of partition table
I (111) esp_image: segment 0: paddr=00010020 vaddr=3c0a0020 size=3d23ch (250428) map
I (158) esp_image: segment 1: paddr=0004d264 vaddr=3fc8f230 size=010a0h (  4256) load
I (159) esp_image: segment 2: paddr=0004e30c vaddr=3fcc8de8 size=00168h (   360) load
I (164) esp_image: segment 3: paddr=0004e47c vaddr=40378000 size=01b9ch (  7068) load
I (174) esp_image: segment 4: paddr=00050020 vaddr=42000020 size=92168h (598376) map
I (271) esp_image: segment 5: paddr=000e2190 vaddr=40379b9c size=05690h ( 22160) load
I (279) boot: Loaded app from partition at offset 0x10000
I (279) boot: Disabling RNG early entropy source...

This section in the api guide includes:

The First Stage Bootloader in ROM reads the Second Stage Bootloader header information from flash and uses this information to load the rest of the Second Stage Bootloader from flash. However, at this time the system clock speed is lower than configured and not all flash modes are supported.

Also esp-idf seems to mark the bootloader as DIO when you have specified QIO.

liebman commented 1 month ago

More info found here that confirms that the bootloader should be marked as DIO even for QIO.

For example, on ESP32 if ESP-IDF is configured for qio/qout mode then the IDF software bootloader is actually flashed with a dio/dout mode. When ROM code boots this bootloader from flash, the bootloader software checks the flash chip model and enables the correct Quad SPI mode for the rest of the boot process. This is because of the multiple different ways to enable Quad SPI on different chip models.