Targets for esp32s3

[ivmarkov]

Given that the ESP-IDF master branch does support esp32s3, perhaps it is time to add the two relevant targets to the compiler as well (the *-espidf one as well as the bare-metal one).

I would assume the S3 chip is supported by the Espressif LLVM fork in the meantime, right?

[MabezDev]

Correct,

./llc llc -march=xtensa -mattr=help
Available CPUs for this target:

  esp32    - Select the esp32 processor.
  esp32-s2 - Select the esp32-s2 processor.
  esp32-s3 - Select the esp32-s3 processor.
  esp8266  - Select the esp8266 processor.
  generic  - Select the generic processor.

Available features for this target:

  atomctl           - Enable Xtensa ATOMCTL option.
  bool              - Enable Xtensa Boolean extension.
  coprocessor       - Enable Xtensa Coprocessor option.
  debug             - Enable Xtensa Debug option.
  density           - Enable Density instructions.
  dfpaccel          - Enable Xtensa Double Precision FP acceleration.
  div32             - Enable Xtensa Div32 option.
  esp32s2           - Support Xtensa esp32-s2 ISA extension.
  esp32s3           - Support Xtensa esp32-s3 ISA extension.
  exception         - Enable Xtensa Exception option.
  extendedl32r      - Enable Xtensa Extended L32R option.
  fp                - Enable Xtensa Single FP instructions.
  highpriinterrupts - Enable Xtensa HighPriInterrupts option.
  interrupt         - Enable Xtensa Interrupt option.
  loop              - Enable Xtensa Loop extension.
  mac16             - Enable Xtensa MAC16 instructions.
  memctl            - Enable Xtensa MEMCTL option.
  miscsr            - Enable Xtensa Miscellaneous SR option.
  mul32             - Enable Xtensa Mul32 option.
  mul32high         - Enable Xtensa Mul32High option.
  nsa               - Enable Xtensa NSA option.
  prid              - Enable Xtensa Processor ID option.
  regprotect        - Enable Xtensa Region Protection option.
  rvector           - Enable Xtensa Relocatable Vector option.
  s32c1i            - Enable Xtensa S32C1I option.
  sext              - Enable Xtensa Sign Extend option.
  threadptr         - Enable Xtensa THREADPTR option.
  timerint          - Enable Xtensa Timer Interrupt option.
  windowed          - Enable Xtensa Windowed Register option.

Use +feature to enable a feature, or -feature to disable it.
For example, llc -mcpu=mycpu -mattr=+feature1,-feature2

I'll add a idf, and no_std target now.

[ivmarkov]

Mr Obvious here, but these should have CAS enabled. :)

[MabezDev]

Indeed, for once we don't have to worry about atomics. Building on my machine now.

[MabezDev]

Now available in the esp-1.56.0 branch :)