search

espressif / esp-bsp

Board support components for Espressif development boards
Other
205 stars 107 forks source link

Problem after enabling .buff_spiram (BSP-586) #442

Closed hard-cat closed 5 days ago

hard-cat commented 6 days ago

Board

ESP32-S3-WROOM-1 N16R8

Hardware Description

module with connected SPI display (driver GC9A01) ESP-IDF: 5.3.1 LVGL 9.2.2 components used: image

IDE Name

VSCode

Operating System

WIN 10

Description

External memory is connected in the settings, I tried to create an array to check EXT_RAM_BSS_ATTR static uint8_t test[128 * 1024]={0}; // it's work

When trying to use SPI_RAM (.buff_spiram) the software stops working and crashes with the following log:

I (31) boot: ESP-IDF v5.3.1 2nd stage bootloader I (31) boot: compile time Nov 26 2024 19:40:09 I (31) boot: Multicore bootloader I (34) boot: chip revision: v0.2 I (38) boot.esp32s3: Boot SPI Speed : 80MHz I (43) boot.esp32s3: SPI Mode : DIO I (48) boot.esp32s3: SPI Flash Size : 16MB W (52) boot.esp32s3: PRO CPU has been reset by WDT. W (58) boot.esp32s3: APP CPU has been reset by WDT. I (64) boot: Enabling RNG early entropy source... I (69) boot: Partition Table: I (73) boot: ## Label Usage Type ST Offset Length I (80) boot: 0 nvs WiFi data 01 02 00009000 00004000 I (87) boot: 1 phy_init RF data 01 01 0000d000 00001000 I (95) boot: 2 factory factory app 00 00 00010000 00300000 I (102) boot: End of partition table I (107) esp_image: segment 0: paddr=00010020 vaddr=3c070020 size=1926ch (103020) map I (134) esp_image: segment 1: paddr=00029294 vaddr=3fc9c900 size=03774h ( 14196) load I (137) esp_image: segment 2: paddr=0002ca10 vaddr=40378000 size=03608h ( 13832) load I (142) esp_image: segment 3: paddr=00030020 vaddr=42000020 size=6e8e0h (452832) map I (229) esp_image: segment 4: paddr=0009e908 vaddr=4037b608 size=111f4h ( 70132) load I (253) boot: Loaded app from partition at offset 0x10000 I (253) boot: Disabling RNG early entropy source... W (265) flash HPM: HPM mode is optional feature that depends on flash model. Read Docs First! W (265) flash HPM: HPM mode with DC adjustment is disabled. Some flash models may not be supported. Read Docs First! W (274) flash HPM: High performance mode of this flash model hasn't been supported. I (283) MSPI Timing: Flash timing tuning index: 2 I (288) octal_psram: ECC is enabled I (292) octal_psram: vendor id : 0x0d (AP) I (297) octal_psram: dev id : 0x02 (generation 3) I (303) octal_psram: density : 0x03 (64 Mbit) I (309) octal_psram: good-die : 0x01 (Pass) I (314) octal_psram: Latency : 0x01 (Fixed) I (319) octal_psram: VCC : 0x01 (3V) I (324) octal_psram: SRF : 0x01 (Fast Refresh) I (330) octal_psram: BurstType : 0x00 ( Wrap) I (335) octal_psram: BurstLen : 0x03 (1024 Byte) I (341) octal_psram: Readlatency : 0x02 (10 cycles@Fixed) I (347) octal_psram: DriveStrength: 0x00 (1/1) I (358) MSPI Timing: PSRAM timing tuning index: 2 I (358) esp_psram: Found 8MB PSRAM device I (363) esp_psram: Speed: 120MHz I (367) cpu_start: Multicore app I (628) esp_psram: SPI SRAM memory test OK I (637) cpu_start: Pro cpu start user code I (637) cpu_start: cpu freq: 240000000 Hz I (637) app_init: Application information: I (640) app_init: Project name: c_rem_47mm I (645) app_init: App version: 1 I (650) app_init: Compile time: Nov 26 2024 19:39:29 I (656) app_init: ELF file SHA256: 08229047a... I (661) app_init: ESP-IDF: v5.3.1 I (666) efuse_init: Min chip rev: v0.0 I (670) efuse_init: Max chip rev: v0.99 I (675) efuse_init: Chip rev: v0.2 I (680) heap_init: Initializing. RAM available for dynamic allocation: I (687) heap_init: At 3FCB0C80 len 00038A90 (226 KiB): RAM I (694) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM I (700) heap_init: At 600FE100 len 00001EE8 (7 KiB): RTCRAM I (706) esp_psram: Adding pool of 7677K of PSRAM memory to heap allocator I (714) spi_flash: detected chip: generic I (718) spi_flash: flash io: dio W (722) i2c: This driver is an old driver, please migrate your application code to adapt driver/i2c_master.h I (733) sleep: Configure to isolate all GPIO pins in sleep state I (740) sleep: Enable automatic switching of GPIO sleep configuration I (747) main_task: Started on CPU0 I (757) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations I (757) main_task: Calling app_main() I (767) gpio: GPIO[46]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 I (777) EXAMPLE: Install panel IO I (777) gpio: GPIO[11]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 D (787) lcd_panel.io.spi: new spi lcd panel io @0x3fcc0174, max_trans_bytes: 32768 I (797) EXAMPLE: Install GC9A01 panel driver I (797) gpio: GPIO[35]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 I (807) gc9a01: LCD panel create success, version: 2.0.0 D (937) lcd_panel.io.i2c: new i2c lcd panel io @0x3fcc0870 I (937) gpio: GPIO[21]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:2 I (937) gpio: GPIO[47]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 I (1347) CST816S: IC id: 182 I (1347) LVGL: Starting LVGL task ESP-ROM:esp32s3-20210327 Build:Mar 27 2021 rst:0x8 (TG1WDT_SYS_RST),boot:0x2f (SPI_FAST_FLASH_BOOT) Saved PC:0x40379b06 --- 0x40379b06: xt_highint4 at C:/Users/mcdim/esp/v5.3.1/esp-idf/components/esp_system/port/soc/esp32s3/highint_hdl.S:49

with the setting for using spir_ram disabled, the sketch starts and works, and displays the image

Sketch

    /* Add LCD screen */
    ESP_LOGD(TAG, "Add LCD screen");
    const lvgl_port_display_cfg_t disp_cfg = {
        .io_handle = lcd_io,
        .panel_handle = lcd_panel,
        .buffer_size = EXAMPLE_LCD_H_RES * EXAMPLE_LCD_DRAW_BUFF_HEIGHT,
        //.trans_size = 64,
        .double_buffer = true,
        .hres = EXAMPLE_LCD_H_RES,
        .vres = EXAMPLE_LCD_V_RES,
        .monochrome = false,
        .color_format = LV_COLOR_FORMAT_RGB565,
        .rotation = {
            .swap_xy = false,
            .mirror_x = false,
            .mirror_y = true,
        },
        .flags = {
            .swap_bytes = true,
            .buff_dma = true,
           // .buff_spiram = true,
        }
    };
    lvgl_disp = lvgl_port_add_disp(&disp_cfg);

Other Steps to Reproduce

It seems that one of the two buffers will have time to write to the display before the application stops. I tried to turn off "double_buffer" - it didn't work. Set the flash memory frequency to 80 and 120 MHz - no changes. I also previously worked with previous versions of LVGL and ESP-IDF, using the attribute I placed the array in SPIRAM in this way and everything worked out:

/*Allocate a large array to store the dynamically allocated data*/
EXT_RAM_ATTR static LV_MEM_ATTR MEM_UNIT work_mem_int[LV_MEM_SIZE / sizeof(MEM_UNIT)];

Now, when trying to do the same thing, the code stops working, the application crashes

/*Allocate a large array to store the dynamically allocated data*/
EXT_RAM_BSS_ATTR static LV_ATTRIBUTE_LARGE_RAM_ARRAY MEM_UNIT work_mem_int[LV_MEM_SIZE / sizeof(MEM_UNIT)];

I have checked existing issues, README.md and ESP32 Forum

hard-cat commented 5 days ago

I found the reason, it was my mistake. In this module there is an octal spiram, which uses ports 35-37, which were connected to the periphery, disconnecting these pins from the module solved the problem with freezing.