CH395 is the first domestic Ethernet controller that supports 10M/100M and has a built-in TCP/IP protocol stack. It was designed by NanjingQinhengMicroelectronics CO LTD (abbreviated as WCH) and officially launched on March 1, 2013. In terms of functionality, ch395 is comparable to Wiznet W5500. In addition, this chip can also use UART to communicate, which has fewer lines than SPI.
However, WCH only provides sample code on 80C51. What's worse, sample code is more focus on hardware TCP/IP stack of the chip. Introductions about MAC Raw mode are pretty brief. This seriously hinders its compatibility with the lwip.
My work is to explore the functionality of the chip in MAC RAW mode and port it into the esp-eth-drivers. As far as I know, no one has ever done that.
High Lights
SPI and UART dual stack support
UART automatic baudrate configuration(refer to README in detail)
Static cache to store fragmented data generated during transmission and reception
Optimization of frequently used function
Passed 5 hours iperf stability test with no error
Issue & Solution
Cannot send pack less than 60 bytes in MAC RAW mode. Just padding 0 to these packs before transferring to CH395
Cannot accept continuous R/W in SPI Mode. R/W one byte per transaction.
Send CMD01_GET_CMD_STATUS before the CH395 init, the status is keeping CH395_ERR_BUSY. Leave enough waiting time for some operations that require query to avoid queries.
Fail to init CH395 after sending CMD40_SET_FUN_PARA to disable SEND_OK interrupt. Add additional delay(20 ms)
After sending CMD10_SET_PHY to setup mode of PHY, within a short period of time, user would get unknow status of PHY(using CMD01_GET_PHY_STATUS). Add additional delay(350 ms)
Performance Report
UART Mode
Baudrate(bps)
TCP Receive(Mbps)
UDP Send(Mbps)
3000000
1.8
1.94
1500000
0.92
0.99
921600
0.54
0.61
460800
0.28
0.30
250000
0.15
0.16
Both transmit and receive increase LINEARLY as the baudrate increases. That fully demonstrates that the system bottleneck is not in the driver layer, but in baudrate instead.
SPI Mode
Frequency(MHz)
TCP Receive(Mbps)
UDP Send(Mbps)
40(OC)
0.54
0.58
30
0.53
0.57
20
0.53
0.57
16
0.50
0.53
10
0.51
0.55
4
0.46
0.49
1
0.30
0.32
The sending and receiving speed gradually becomes saturated after the SPI frequency is higher than 10MHz. This is mainly because the chip cannot support SPI continuous reading and writing, and a certain delay must be added between bytes, which makes DMA useless. I have already sent my questions to WCH engineers and hope to get a reply soon. On the other hand, someone could provide me with some valuable advice on SPI transmission if possible?
After Optimization
Frequency(MHz)
TCP Receive(Mbps)
UDP Send(Mbps)
20
1.63
13.58
16
1.55
11.47
10
0.95
7.82
Optimization is based on the following "features":
At frequency below 20MHz, 4 bytes of continuous reading of SRAM is correct. Thus, in ch395_rx_buffer, packet reads are performed in 4-byte increments to improve efficiency. I guess this may be due to the SRAM's synchronization mechanism.
Continuous writing of SRAM has no issue. Thus, in ch395_tx_buffer, packet writings are performed in one transmission. That's why TX Performance has been greatly improved.
However, register reading cannot be continuous. I tried frequency below 10MHz to read MAC addresses continuously. Only the first byte is correct. Therefore, ch395_spi_io operations are as legacy.
PS:
Here is the introduction to this ethernet controller in detail:
CH395 is an Ethernet protocol stack management IC which provides Ethernet communication ability for MCU system. CH395 has built-in 10 / 100M Ethernet MAC and PHY and fully compatible with IEEE 802.3 protocol, it also has built-in protocol stack firmware such as PPPOE, IP, DHCP, ARP, ICMP, IGMP, UDP, TCP and etc. A MCU system can easily connect to Ethernet through CH395. CH395 supports 3 types of communication interfaces: 8-bit parallel port, SPI or USART. A MCU/DSP/MPU can use any of the above communication interfaces to operate CH395 for Ethernet communication.
Brief Introduction
CH395 is the first domestic Ethernet controller that supports 10M/100M and has a built-in TCP/IP protocol stack. It was designed by NanjingQinhengMicroelectronics CO LTD (abbreviated as WCH) and officially launched on March 1, 2013. In terms of functionality, ch395 is comparable to Wiznet W5500. In addition, this chip can also use UART to communicate, which has fewer lines than SPI.
However, WCH only provides sample code on 80C51. What's worse, sample code is more focus on hardware TCP/IP stack of the chip. Introductions about MAC Raw mode are pretty brief. This seriously hinders its compatibility with the lwip.
My work is to explore the functionality of the chip in MAC RAW mode and port it into the
esp-eth-drivers. As far as I know, no one has ever done that.High Lights
Issue & Solution
Cannot accept continuous R/W in SPI Mode. R/W one byte per transaction.CMD01_GET_CMD_STATUSbefore the CH395 init, the status is keepingCH395_ERR_BUSY. Leave enough waiting time for some operations that require query to avoid queries.CMD40_SET_FUN_PARAto disableSEND_OKinterrupt. Add additional delay(20 ms)CMD10_SET_PHYto setup mode of PHY, within a short period of time, user would get unknow status of PHY(usingCMD01_GET_PHY_STATUS). Add additional delay(350 ms)Performance Report
UART Mode
Both transmit and receive increase LINEARLY as the baudrate increases. That fully demonstrates that the system bottleneck is not in the driver layer, but in baudrate instead.
SPI Mode
The sending and receiving speed gradually becomes saturated after the SPI frequency is higher than 10MHz. This is mainly because the chip cannot support SPI continuous reading and writing, and a certain delay must be added between bytes, which makes DMA useless. I have already sent my questions to WCH engineers and hope to get a reply soon. On the other hand, someone could provide me with some valuable advice on SPI transmission if possible?
Optimization is based on the following "features":
ch395_rx_buffer, packet reads are performed in 4-byte increments to improve efficiency. I guess this may be due to the SRAM's synchronization mechanism.ch395_tx_buffer, packet writings are performed in one transmission. That's why TX Performance has been greatly improved.ch395_spi_iooperations are as legacy.PS: Here is the introduction to this ethernet controller in detail: CH395 is an Ethernet protocol stack management IC which provides Ethernet communication ability for MCU system. CH395 has built-in 10 / 100M Ethernet MAC and PHY and fully compatible with IEEE 802.3 protocol, it also has built-in protocol stack firmware such as PPPOE, IP, DHCP, ARP, ICMP, IGMP, UDP, TCP and etc. A MCU system can easily connect to Ethernet through CH395. CH395 supports 3 types of communication interfaces: 8-bit parallel port, SPI or USART. A MCU/DSP/MPU can use any of the above communication interfaces to operate CH395 for Ethernet communication.