Open HikingDev opened 3 years ago
Hello @HikingDev We checked the analyser and it seems that CS being high, But while actual transfer, it goes low as expected and then only clock is released.
So, Actual transfers are handled correctly.
This CS is handled by ST's NSS. and we do not have much control over it. Other way to handle this is manual CS control.
Hello @mantriyogesh ,
was the test performed with the WROOM-32E?
It seems that the stm32f.. output is unable to set GPIO5 CS of the WROOM-32E to low.
Since there is only one slave I have tried to change line 500 in spi_slave_api.c
to GPIO_PULLDOWN_ONLY. This test was successful.
Hi,
the ESP32 hotsted project worked fine with the ESP32 WROVER Kit Development board and the ESP32-WROVER_B and the STM32F469NIH. Now we tried running esp-hosted project with STM32F469NIH an the ESP32-DevKitC (ESP32-WROOM-32E). The logic Analyzer shows that GPIO5 (CS) stays permanently high. In the datasheet the GPIO5 is marked as a strapping pin and also must be HIGH on bootup. I have however tried to set GPIO5 to low in host code after the reset, without success. Any hints?