espressif / esp-idf

Espressif IoT Development Framework. Official development framework for Espressif SoCs.
Apache License 2.0
13.61k stars 7.27k forks source link

W5500 ETH - Host name doesn't get set properly (IDFGH-11500) #12627

Closed Flamabalistic closed 9 months ago

Flamabalistic commented 11 months ago

Answers checklist.

IDF version.

v5.1

Espressif SoC revision.

ESP32-S3

Operating System used.

Windows

How did you build your project?

VS Code IDE

If you are using Windows, please specify command line type.

None

Development Kit.

Custom PCB

Power Supply used.

USB

What is the expected behavior?

What is the actual behavior?

Steps to reproduce.

Short version:

Long version:

Below is all of the relevant code, with w5500_init being ran on start-up

static const char *TAG = "W5500 eth";

#include "esp_log.h"
#include "esp_netif.h"
#include "esp_event.h"
#include "driver/gpio.h"

#include <string.h>

#include "esp_mac.h"
#include "esp_eth_mac.h"
#include "esp_eth_driver.h"
#include "esp_eth_netif_glue.h"
#include "driver/spi_common.h"
#include "driver/spi_master.h" // https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/peripherals/spi_master.html
#include "lwip/inet.h"
#include "interfaces/tcp/tcp_common.hpp"

#include "triggermodule/settings.h"

// W5500 Pin assignments
#define MOSI_GPIO GPIO_NUM_33
#define MISO_GPIO GPIO_NUM_34
#define SCLK_GPIO GPIO_NUM_35
#define CS_GPIO GPIO_NUM_36
#define INT_GPIO GPIO_NUM_26
#define RST_GPIO GPIO_NUM_21

esp_netif_ip_info_t s_ip_info;
esp_eth_handle_t eth_handle_spi = NULL;
esp_netif_t *eth_netif_spi = NULL;

static void EthernetHardwareEventHandler(void *arg, esp_event_base_t event_base,
                                         int32_t event_id, void *event_data)
{
    uint8_t mac_addr[6] = {0};
    esp_eth_handle_t eth_handle = *(esp_eth_handle_t *)event_data;

    switch (event_id)
    {
    case ETHERNET_EVENT_CONNECTED:
        esp_eth_ioctl(eth_handle, ETH_CMD_G_MAC_ADDR, mac_addr);
        ESP_LOGI(TAG, "Ethernet Link Up");
        ESP_LOGD(TAG, "Ethernet HW Addr %02x:%02x:%02x:%02x:%02x:%02x",
                 mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);

        // set static ip
        if (settings->eth_static_ip_enabled)
        {
            esp_netif_ip_info_t ip_info;
            inet_aton(settings->eth_static_ip.data(), &ip_info.ip);
            inet_aton(settings->eth_gateway.data(), &ip_info.gw);
            inet_aton(settings->eth_netmask.data(), &ip_info.netmask);
            esp_netif_dhcpc_stop(eth_netif_spi);
            esp_netif_set_ip_info(eth_netif_spi, &ip_info);
        }
        break;
    case ETHERNET_EVENT_DISCONNECTED:
        ESP_LOGI(TAG, "Ethernet Link Down");
        break;
    case ETHERNET_EVENT_START:
        ESP_LOGI(TAG, "Ethernet Started");
        break;
    case ETHERNET_EVENT_STOP:
        ESP_LOGI(TAG, "Ethernet Stopped");
        break;
    default:
        ESP_LOGI(TAG, "Unhandled event encountered with id: %ld", event_id);
        break;
    }
}

static void GetIpEventHandler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data)
{
    ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data;
    const esp_netif_ip_info_t *ip_info = &event->ip_info;

    ESP_LOGI(TAG, "Ethernet Got IP Address");
    ESP_LOGI(TAG, "~~~~~~~~~~~");
    ESP_LOGI(TAG, "ETHIP:" IPSTR, IP2STR(&ip_info->ip));
    ESP_LOGI(TAG, "ETHMASK:" IPSTR, IP2STR(&ip_info->netmask));
    ESP_LOGI(TAG, "ETHGW:" IPSTR, IP2STR(&ip_info->gw));
    ESP_LOGI(TAG, "~~~~~~~~~~~");
    memcpy(&s_ip_info, &event->ip_info, sizeof(s_ip_info));
}

void w5500_init(bool is_enabled)
{
    if (!is_enabled)
        return;
    //  Create instance(s) of esp-netif for SPI Ethernet(s)
    esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH();
    esp_netif_config_t cfg_spi = {
        .base = &esp_netif_config,
        .stack = ESP_NETIF_NETSTACK_DEFAULT_ETH};

    char if_key_str[10];
    char if_desc_str[10];
    int num = 0;
    sprintf(if_key_str, "ETH_SPI_%d", num);
    sprintf(if_desc_str, "eth%d", num);

    ESP_LOGD(TAG, "Creating eth_netif_spi");
    esp_netif_config.if_key = if_key_str;
    esp_netif_config.if_desc = if_desc_str;
    esp_netif_config.route_prio = 30;
    eth_netif_spi = esp_netif_new(&cfg_spi);
    ESP_ERROR_CHECK(esp_netif_set_hostname(eth_netif_spi, tcp_get_hostname().c_str()));

    // Init MAC and PHY configs to default
    eth_mac_config_t mac_config_spi = ETH_MAC_DEFAULT_CONFIG();
    mac_config_spi.rx_task_stack_size = 16384;
    eth_phy_config_t phy_config_spi = ETH_PHY_DEFAULT_CONFIG();
    phy_config_spi.autonego_timeout_ms = 0;
    phy_config_spi.reset_gpio_num = -1;

    ESP_LOGD(TAG, "Installing isr service");
    gpio_install_isr_service(0);

    // Init SPI bus
    spi_bus_config_t buscfg = {
        .mosi_io_num = MOSI_GPIO,
        .miso_io_num = MISO_GPIO,
        .sclk_io_num = SCLK_GPIO,
        .quadwp_io_num = -1,
        .quadhd_io_num = -1,
    };
    ESP_LOGD(TAG, "Initializing SPI bus");
    ESP_ERROR_CHECK(spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO));

    // Configure SPI interface and Ethernet driver for specific SPI module
    esp_eth_mac_t *mac_spi;
    esp_eth_phy_t *phy_spi;
    spi_device_interface_config_t spi_devcfg = {
        .command_bits = 16, // Actually it's the address phase in W5500 SPI frame
        .address_bits = 8,  // Actually it's the control phase in W5500 SPI frame
        .mode = 0,
        .clock_speed_hz = 16 * 1000 * 1000,
        .spics_io_num = CS_GPIO,
        .queue_size = 20};

    // Set remaining GPIO numbers and configuration used by the SPI module
    phy_config_spi.phy_addr = 1;

    eth_w5500_config_t w5500_config = ETH_W5500_DEFAULT_CONFIG(SPI2_HOST, &spi_devcfg);
    w5500_config.int_gpio_num = INT_GPIO;
    ESP_LOGD(TAG, "Setting up w5500 mac");
    mac_spi = esp_eth_mac_new_w5500(&w5500_config, &mac_config_spi);
    ESP_LOGD(TAG, "Setting up w5500 phy");
    phy_spi = esp_eth_phy_new_w5500(&phy_config_spi);
    ESP_LOGD(TAG, "Finished setting up w5500 phy");

    vTaskDelay(pdMS_TO_TICKS(10)); // wait for w5500 to startup - causes `invalid chip version, expected 0x4, actual 0x0` otherwise

    esp_eth_config_t eth_config_spi = ETH_DEFAULT_CONFIG(mac_spi, phy_spi);

    ESP_LOGD(TAG, "Installing ETH driver");
    ESP_ERROR_CHECK(esp_eth_driver_install(&eth_config_spi, &eth_handle_spi));

    uint8_t mac_addr[6];
    ESP_LOGD(TAG, "Setting ethernet mac");
    ESP_ERROR_CHECK(esp_read_mac(mac_addr, ESP_MAC_ETH));
    ESP_ERROR_CHECK(esp_eth_ioctl(eth_handle_spi, ETH_CMD_S_MAC_ADDR, mac_addr));

    ESP_LOGD(TAG, "Attaching ethernet driver to TCP/IP stack");
    ESP_ERROR_CHECK(esp_netif_attach(eth_netif_spi, esp_eth_new_netif_glue(eth_handle_spi)));

    ESP_LOGD(TAG, "Register user defined ethernet event handers");
    ESP_ERROR_CHECK(esp_event_handler_register(ETH_EVENT, ESP_EVENT_ANY_ID, &EthernetHardwareEventHandler, NULL));
    ESP_ERROR_CHECK(esp_event_handler_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, &GetIpEventHandler, NULL));

    ESP_LOGD(TAG, "Starting ethernet driver state machine");
    ESP_ERROR_CHECK(esp_eth_start(eth_handle_spi));
}

Debug Logs.

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DOUT, clock div:1
load:0x3fce3818,len:0x16e4
load:0x403c9700,len:0x4
load:0x403c9704,len:0xc00
load:0x403cc700,len:0x2ed0
entry 0x403c9908
I (27) boot: ESP-IDF v5.1-dirty 2nd stage bootloader
I (27) boot: compile time Nov 10 2023 09:10:04
I (27) boot: Multicore bootloader
I (30) boot: chip revision: v0.1
I (34) boot.esp32s3: Boot SPI Speed : 80MHz
I (39) boot.esp32s3: SPI Mode       : DOUT
I (44) boot.esp32s3: SPI Flash Size : 8MB
I (49) boot: Enabling RNG early entropy source...
I (54) boot: Partition Table:
I (58) boot: ## Label            Usage          Type ST Offset   Length
I (65) boot:  0 nvs              WiFi data        01 02 0000d000 00004000
I (72) boot:  1 otadata          OTA data         01 00 00011000 00002000
I (80) boot:  2 phy_init         RF data          01 01 00013000 00001000
I (87) boot:  3 ota_0            OTA app          00 10 00020000 00180000
I (95) boot:  4 ota_1            OTA app          00 11 001a0000 00180000
I (102) boot: End of partition table
I (107) esp_image: segment 0: paddr=00020020 vaddr=3c070020 size=3f0bch (258236) map
I (165) esp_image: segment 1: paddr=0005f0e4 vaddr=3fc95e00 size=00f34h (  3892) load
I (166) esp_image: segment 2: paddr=00060020 vaddr=42000020 size=6c418h (443416) map
I (255) esp_image: segment 3: paddr=000cc440 vaddr=3fc96d34 size=02414h (  9236) load
I (258) esp_image: segment 4: paddr=000ce85c vaddr=40374000 size=11d50h ( 73040) load
I (286) boot: Loaded app from partition at offset 0x20000
I (291) boot: Disabling RNG early entropy source...
I (297) cpu_start: Multicore app
D (297) flash HPM: HPM with dummy, status is 1
I (297) flash HPM: Enabling flash high speed mode by dummy
D (301) flash HPM: Checking whether HPM has been executed
D (306) MSPI Timing: 0, bad
D (309) MSPI Timing: 1, good
D (312) MSPI Timing: 2, good
D (315) MSPI Timing: 3, good
D (318) MSPI Timing: 4, bad
D (321) MSPI Timing: 5, bad
D (323) MSPI Timing: 6, bad
D (326) MSPI Timing: 7, bad
D (329) MSPI Timing: 8, bad
D (332) MSPI Timing: 9, bad
D (335) MSPI Timing: 10, bad
D (338) MSPI Timing: 11, bad
W (341) FLASH/PSRAM: DO NOT USE FOR MASS PRODUCTION! Timing parameters may be updated in future IDF version.
D (351) MSPI Timing: tuning success, best point is index 2
I (357) cpu_start: Pro cpu up.
I (362) cpu_start: Starting app cpu, entry point is 0x403756cc
I (0) cpu_start: App cpu up.
D (376) clk: RTC_SLOW_CLK calibration value: 3454208
I (388) cpu_start: Pro cpu start user code
I (388) cpu_start: cpu freq: 160000000 Hz
I (388) cpu_start: Application information:
I (391) cpu_start: Project name:     xxx
I (397) cpu_start: App version:      10de4ed-dirty
I (402) cpu_start: Compile time:     Nov 17 2023 17:06:56
I (408) cpu_start: ELF file SHA256:  ebc1c100b5418208...
I (414) cpu_start: ESP-IDF:          v5.1-dirty
I (420) cpu_start: Min chip rev:     v0.0
I (424) cpu_start: Max chip rev:     v0.99
I (429) cpu_start: Chip rev:         v0.1
D (434) memory_layout: Checking 5 reserved memory ranges:
D (439) memory_layout: Reserved memory range 0x3fc84000 - 0x3fc95e00
D (446) memory_layout: Reserved memory range 0x3fc95e00 - 0x3fc9add0
D (452) memory_layout: Reserved memory range 0x3fceee34 - 0x3fcf0000
D (459) memory_layout: Reserved memory range 0x40374000 - 0x40385e00
D (465) memory_layout: Reserved memory range 0x600fe000 - 0x600fe010
D (471) memory_layout: Building list of available memory regions:
D (478) memory_layout: Available memory region 0x3fc9add0 - 0x3fca0000
D (484) memory_layout: Available memory region 0x3fca0000 - 0x3fcb0000
D (491) memory_layout: Available memory region 0x3fcb0000 - 0x3fcc0000
D (497) memory_layout: Available memory region 0x3fcc0000 - 0x3fcd0000
D (504) memory_layout: Available memory region 0x3fcd0000 - 0x3fce0000
D (511) memory_layout: Available memory region 0x3fce0000 - 0x3fce9710
D (517) memory_layout: Available memory region 0x3fce9710 - 0x3fceee34
D (524) memory_layout: Available memory region 0x3fcf0000 - 0x3fcf8000
D (530) memory_layout: Available memory region 0x600fe010 - 0x60100000
I (537) heap_init: Initializing. RAM available for dynamic allocation:
D (544) heap_init: New heap initialised at 0x3fc9add0
I (549) heap_init: At 3FC9ADD0 len 0004E940 (314 KiB): DRAM
I (556) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
D (562) heap_init: New heap initialised at 0x3fcf0000
I (567) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
D (574) heap_init: New heap initialised at 0x600fe010
I (579) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
D (585) intr_alloc: Connected src 39 to int 2 (cpu 0)
D (591) spi_flash: trying chip: issi
D (594) spi_flash: trying chip: gd
I (597) spi_flash: detected chip: gd
I (601) spi_flash: flash io: dio
D (605) cpu_start: calling init function: 0x42055a94
D (611) cpu_start: calling init function: 0x420558cc
D (616) cpu_start: calling init function: 0x42047694
D (621) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (627) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (634) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (641) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (648) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (655) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
D (662) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (669) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (676) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (683) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (690) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (697) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
D (704) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (711) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (718) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (725) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (732) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (739) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
D (746) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (753) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (760) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (767) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (774) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (781) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
D (788) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (795) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (802) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (809) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (816) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (823) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
D (830) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (837) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (844) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (851) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (858) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (865) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
D (872) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (879) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (886) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (893) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (900) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (907) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
D (914) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (920) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (928) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (935) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (942) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (949) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
D (955) cpu_start: calling init function: 0x42029570
D (961) cpu_start: calling init function: 0x4201f3b0
D (966) cpu_start: calling init function: 0x4201eee4
D (971) cpu_start: calling init function: 0x4201862c
D (976) cpu_start: calling init function: 0x42002e6c
D (981) cpu_start: calling init function: 0x42008024 on core: 0
D (987) intr_alloc: Connected src 59 to int 3 (cpu 0)
D (992) cpu_start: calling init function: 0x42005a24 on core: 0
I (998) sleep: Configure to isolate all GPIO pins in sleep state
I (1005) sleep: Enable automatic switching of GPIO sleep configuration
D (1012) cpu_start: calling init function: 0x42003fd4 on core: 0
D (1018) cpu_start: Setting C++ exception workarounds.
D (1023) intr_alloc: Connected src 79 to int 9 (cpu 0)
I (1028) app_start: Starting scheduler on CPU0
D (1033) intr_alloc: Connected src 57 to int 12 (cpu 0)
D (1033) intr_alloc: Connected src 80 to int 2 (cpu 1)
I (1043) app_start: Starting scheduler on CPU1
D (1043) intr_alloc: Connected src 58 to int 3 (cpu 1)
I (1033) main_task: Started on CPU0
D (1053) heap_init: New heap initialised at 0x3fce9710
D (1053) intr_alloc: Connected src 52 to int 13 (cpu 0)
I (1063) main_task: Calling app_main()
I (1063) Main app: app_main() started
I (1073) Main app: Initializing app
D (1073) event: running task for loop 0x3fca30c8
D (1083) event: created task for loop 0x3fca30c8
D (1083) event: created event loop 0x3fca30c8
I (1103) NVS: Opening Non-Volatile Storage (NVS) handle
I (1103) NVS: Finished initializing NVS flash
I (1103) Settings: Initializing settings
I (1103) Settings: quick_reset = false
I (1113) Settings: Finished initializing settings
D (1113) NVS: err: 0, len: 1372
D (1383) efuse: In EFUSE_BLK1__DATA1_REG is used 8 bits starting with 8 bit
D (1393) efuse: In EFUSE_BLK1__DATA1_REG is used 8 bits starting with 0 bit
D (1393) efuse: In EFUSE_BLK1__DATA0_REG is used 8 bits starting with 24 bit
D (1403) efuse: In EFUSE_BLK1__DATA0_REG is used 8 bits starting with 16 bit
D (1413) efuse: In EFUSE_BLK1__DATA0_REG is used 8 bits starting with 8 bit
D (1423) efuse: In EFUSE_BLK1__DATA0_REG is used 8 bits starting with 0 bit
D (1643) gdma: new group (0) at 0x3fca84c4
D (1643) gdma: new pair (0,0) at 0x3fca8508
D (1653) gdma: new rx channel (0,0) at 0x3fca8490
D (1653) intr_alloc: Connected src 66 to int 17 (cpu 0)
D (1663) gdma: install interrupt service for rx channel (0,0)
I (1663) gpio: GPIO[10]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
D (1673) ADC: creating curve fitting calibration scheme
D (1683) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (1683) efuse: In EFUSE_BLK2__DATA6_REG is used 8 bits starting with 9 bit
D (1693) efuse: In EFUSE_BLK2__DATA6_REG is used 8 bits starting with 17 bit
D (1703) efuse: In EFUSE_BLK2__DATA6_REG is used 7 bits starting with 25 bit
D (1703) efuse: In EFUSE_BLK2__DATA7_REG is used 1 bits starting with 0 bit
D (1713) efuse: In EFUSE_BLK2__DATA7_REG is used 8 bits starting with 1 bit
D (1723) efuse: In EFUSE_BLK2__DATA7_REG is used 8 bits starting with 9 bit
D (1733) efuse: In EFUSE_BLK2__DATA7_REG is used 7 bits starting with 17 bit
D (1733) efuse: In EFUSE_BLK2__DATA7_REG is used 7 bits starting with 24 bit
D (1743) efuse: In EFUSE_BLK1__DATA5_REG is used 6 bits starting with 26 bit
D (1793) ledc: Using clock source 4 (in slow mode), divisor: 0x42b
D (1793) ledc: In slow speed mode, global clk set: 4
D (1803) ledc: LEDC_PWM CHANNEL 0|GPIO 40|Duty 0000|Time 0
D (1813) esp_netif_lwip: LwIP stack has been initialized
D (1823) esp_netif_lwip: esp-netif has been successfully initialized
D (2073) W5500 eth: Creating eth_netif_spi
D (2083) esp_netif_objects: esp_netif_add_to_list 0x3fcad430
D (2083) esp_netif_objects: esp_netif_add_to_list netif added successfully (total netifs: 1)
D (2093) esp_netif_lwip: check: remote, if=0x0 fn=0x42044f5c

D (2103) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (2123) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x42045a74

D (2123) esp_netif_lwip: esp_netif_set_hostname_api esp_netif:0x3fcad430 hostname UMD-M320-574B50A8D134
D (2133) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (2143) W5500 eth: esp_netif_is_netif_up: f
D (2143) W5500 eth: Installing isr service
D (2153) intr_alloc: Connected src 16 to int 19 (cpu 0)
D (2153) W5500 eth: Initializing SPI bus
D (2163) gdma: new pair (0,1) at 0x3fcad8ac
D (2163) gdma: new tx channel (0,1) at 0x3fcad878
D (2163) gdma: new rx channel (0,1) at 0x3fcad8cc
D (2173) spi: SPI2 use gpio matrix.
D (2173) W5500 eth: Setting up w5500 mac
D (2183) intr_alloc: Connected src 21 to int 20 (cpu 0)
D (2183) spi_hal: eff: 16000, limit: 80000k(/0), 0 dummy, -1 delay
D (2193) spi_master: SPI2: New device added to CS0, effective clock: 16000kHz
D (2203) W5500 eth: Setting up w5500 phy
D (2203) W5500 eth: Finished setting up w5500 phy
D (2213) W5500 eth: Installing ETH driver
D (2223) esp_eth: new ethernet driver @0x3fcb2604
D (2223) W5500 eth: Setting ethernet mac
D (2223) W5500 eth: Attaching ethernet driver to TCP/IP stack
I (2223) esp_eth.netif.netif_glue: dc:54:75:c4:2a:53
D (2233) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x42044f6c

D (2243) esp_netif_lwip: call api in lwip: ret=0x0, give sem
I (2243) esp_eth.netif.netif_glue: ethernet attached to netif
D (2253) W5500 eth: Register user defined ethernet event handers
D (2253) W5500 eth: Starting ethernet driver state machine
D (2273) event: running post ETH_EVENT:0 with handler 0x420487dc and context 0x3fcb26c4 on loop 0x3fca30c8
D (2273) esp_eth.netif.netif_glue: eth_action_start: 0x3fcb267c, 0x3c09c114, 0, 0x3fcb280c, 0x3fcb2604
D (2283) esp_netif_handlers: esp_netif action has started with netif0x3fcad430 from event_id=0
D (2293) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x420455e4

D (2293) esp_netif_lwip: esp_netif_start_api 0x3fcad430
D (2293) W5500 eth: esp_netif_is_netif_up: f
D (2303) esp_netif_lwip: esp_netif_get_hostname esp_netif:0x3fcad430
D (2313) esp_netif_lwip: check: local, if=0x3fcad430 fn=0x4204624c

D (2323) esp_netif_lwip: esp_netif_update_default_netif_lwip 0x3fcad430
D (2333) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (2343) event: running post ETH_EVENT:0 with handler 0x42017258 and context 0x3fcb27cc on loop 0x3fca30c8
I (2353) W5500 eth: Ethernet Started
D (2363) event: no handlers have been registered for event ESP_HTTP_SERVER_EVENT:1 posted to loop 0x3fca30c8
I (2683) Main app: Finished initializing app
I (2693) main_task: Returned from app_main()
D (4293) event: running post ETH_EVENT:2 with handler 0x42048764 and context 0x3fcb2724 on loop 0x3fca30c8
D (4293) esp_eth.netif.netif_glue: eth_action_connected: 0x3fcb267c, 0x3c09c114, 2, 0x3fcb4de0, 0x3fcb2604
D (4303) esp_netif_handlers: esp_netif action connected with netif0x3fcad430 from event_id=2
D (4313) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x42045af0

D (4323) esp_netif_lwip: esp_netif_up_api esp_netif:0x3fcad430
D (4323) esp_netif_lwip: check: local, if=0x3fcad430 fn=0x4204624c

D (4333) esp_netif_lwip: esp_netif_update_default_netif_lwip 0x3fcad430
D (4343) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (4343) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x42045934

D (4353) esp_netif_lwip: esp_netif_dhcpc_start_api esp_netif:0x3fcad430
D (4363) esp_netif_lwip: esp_netif_start_ip_lost_timer esp_netif:0x3fcad430
D (4363) esp_netif_lwip: if0x3fcad430 start ip lost tmr: no need start because netif=0x3fcad4b4 interval=120 ip=0
D (4373) esp_netif_lwip: starting dhcp client
D (4383) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (4383) event: running post ETH_EVENT:2 with handler 0x42017258 and context 0x3fcb27cc on loop 0x3fca30c8
I (4393) W5500 eth: Ethernet Link Up
D (4403) W5500 eth: Ethernet HW Addr dc:54:75:c4:2a:53
D (4403) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x42045844

D (4413) esp_netif_lwip: esp_netif_dhcpc_stop_api esp_netif:0x3fcad430
D (4423) esp_netif_lwip: esp_netif_start_ip_lost_timer esp_netif:0x3fcad430
D (4423) esp_netif_lwip: if0x3fcad430 start ip lost tmr: no need start because netif=0x3fcad4b4 interval=120 ip=0
D (4433) esp_netif_lwip: dhcp client stop successfully
D (4443) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (4443) esp_netif_lwip: check: remote, if=0x3fcad430 fn=0x42045b40

D (4453) esp_netif_lwip: esp_netif_set_ip_info_api esp_netif:0x3fcad430
D (4463) esp_netif_lwip: esp_netif_internal_dhcpc_cb lwip-netif:0x3fcad4b4
D (4463) esp_netif_lwip: if0x3fcad430 ip unchanged
D (4473) esp_netif_lwip: if0x3fcad430 netif set static ip: ip changed=1
D (4473) esp_netif_lwip: call api in lwip: ret=0x0, give sem
D (4483) event: running post IP_EVENT:4 with handler 0x420486ec and context 0x3fcb2798 on loop 0x3fca30c8
D (4493) esp_eth.netif.netif_glue: eth_action_got_ip: 0x3fcb267c, 0x3c09a2a8, 4, 0x3fcb4df0, 0x3fcad430
D (4503) esp_netif_handlers: esp_netif action got_ip with netif0x3fcad430 from event_id=4
I (4513) esp_netif_handlers: eth0 ip: 192.168.0.93, mask: 255.255.254.0, gw: 192.168.1.253
D (4523) event: running post IP_EVENT:4 with handler 0x42017180 and context 0x3fcb27ec on loop 0x3fca30c8
I (4533) W5500 eth: Ethernet Got IP Address
I (4533) W5500 eth: ~~~~~~~~~~~
I (4543) W5500 eth: ETHIP:192.168.0.93
I (4543) W5500 eth: ETHMASK:255.255.254.0
I (4543) W5500 eth: ETHGW:192.168.1.253
I (4553) W5500 eth: ~~~~~~~~~~~


### More Information.

This is connecting to an enterprise network - which may throw a wrench in something. (I don't know enough about networking to know if that would cause a problem or not)
KaeLL commented 11 months ago

I remember going through this issue myself when testing my w5100 implementation, but I can't recall if I just deemed it not worth bothering, or if an IDF update eventually fixed it.

kostaond commented 11 months ago

Please try to call esp_netif_set_hostname under ETHERNET_EVENT_START event.

Flamabalistic commented 11 months ago

Changed

    case ETHERNET_EVENT_START:
        ESP_LOGI(TAG, "Ethernet Started");
        break;

to

    case ETHERNET_EVENT_START:
        ESP_LOGI(TAG, "Ethernet Started");
        ESP_ERROR_CHECK(esp_netif_set_hostname(eth_netif_spi, "esphost"));
        break;

Still got the same problem. Are there any other logs I can provide that will help diagnose the problem?

kostaond commented 11 months ago

I see what is your problem, now. It's not that simple. You need to properly configure all the services to domain name to IP translation worked properly. Frankly speaking, I'm not expert at this domain, so I can provide you just some generic guidance. Either:

1) Use mDNS.

2) or:

Flamabalistic commented 10 months ago

Sorry for the long wait - been busy with some other features

I can't seem to get mdns working right now, and the other options sadly won't work for my use case (it needs to work with a static ip, and without modifications to the server)

@kostaond I'm no expert in this either, so if esp_netif_set_hostname actually is behaving as expected, feel free to close this issue.

muratdemirtas commented 7 months ago

with new version on v5.2.1 this issue resolved in our side, we have disabled w5500 int pin to do polling method work. IRQ pin = -1 and poll interval were set to 100ms in menuconfig. After that the hostname is apperaing in modem control panel which we set. The ethernet speed is also improved x10 than old interrupt version of ethernet w5500 for OTA and TCP connections.

KaeLL commented 7 months ago

The ethernet speed is also improved x10 than old interrupt version of ethernet w5500 for OTA and TCP connections.

Unrelated, but interesting, especially considering the 100ms RX polling interval. Care to elaborate on this now that you mentioned it?

muratdemirtas commented 7 months ago

The ethernet speed is also improved x10 than old interrupt version of ethernet w5500 for OTA and TCP connections.

Unrelated, but interesting, especially considering the 100ms RX polling interval. Care to elaborate on this now that you mentioned it?

We have multiple designs for w5500 on another projects using with STM32 based MCU's. For new project we decided to make it with ESP32 but we figured out that w5500 driver need interrupt pin to work. (SDK <5.2.1)..

As i mentioned on STM32 based projects, we used poll method to drive w5500 macraw with SOCK0 with 16 kb rx/tx payload buffer. Until this time, we have no issue with w5500, mac address and hostname is everytime set correctly.

But when switched to ESP32, there was a bugs like exists( Hostname set failed, bad TCP performance, OTA takes 3 min for 1.15 mb bin file etc.). We configured w5500 spi pins, reset, irq and cs pin to drive with ESP32 gpios.

#define CONFIG_EXAMPLE_USE_SPI_ETHERNET 1
#define CONFIG_EXAMPLE_SPI_ETHERNETS_NUM 1
#define CONFIG_EXAMPLE_USE_W5500 1
#define CONFIG_EXAMPLE_ETH_SPI_HOST 1
#define CONFIG_EXAMPLE_ETH_SPI_SCLK_GPIO 18
#define CONFIG_EXAMPLE_ETH_SPI_MOSI_GPIO 23
#define CONFIG_EXAMPLE_ETH_SPI_MISO_GPIO 19
#define CONFIG_EXAMPLE_ETH_SPI_CLOCK_MHZ 20
#define CONFIG_EXAMPLE_ETH_SPI_CS0_GPIO 5
#define CONFIG_EXAMPLE_ETH_SPI_INT0_GPIO 36
#define CONFIG_EXAMPLE_ETH_SPI_PHY_RST0_GPIO 25
#define CONFIG_EXAMPLE_ETH_SPI_PHY_ADDR0 1

SCK frequency tested on every frequency ( 20,10,5 Mhz) but TCP performance too bad on ethernet side. I can say that the OTA with ethernet takes 3 - 5 minute for 1.2 mb bin file (sometimes its failed) but wifi takes only 30 seconds to perform OTA. I was know there is anything wrong with our side.

I have waited to poll method support for next SDK's, Today i have upgraded my SDK to v5.2.1 and configured irq pin to -1 and poll interval to 100 ms and ta ta...

OTA and TCP performance improved x10. OTA takes 28 second on ethernet which is perfect. TCP uploads for 1.2 mb takes 12 seconds( without SDK upgrade this was around 1.5 minute).

Hostname is not stable appeared the modem control panel when older SDK. But now is stable.

I just wanted to share that who has that issue.

kostaond commented 7 months ago

The symptoms sound suspicious. Are you sure the interrupt line was properly connected and configured when not using poll mode? The thing is, it could have work even with incorrectly configured INT line because there used to be 1 sec timeout when no INT hit. Therefore, it could explain your poor performance.

    while (1) {
        /* check if the task receives any notification */
        if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000)) == 0 &&    // if no notification ...
            gpio_get_level(emac->int_gpio_num) != 0) {               // ...and no interrupt asserted
            continue;                                                // -> just continue to check again
        }
kostaond commented 7 months ago

The ethernet speed is also improved x10 than old interrupt version

It improved 10 times, 100 ms is 10 times shorter interval than ulTaskNotifyTake 1 sec timeout...

muratdemirtas commented 7 months ago

The ethernet speed is also improved x10 than old interrupt version

It improved 10 times, 100 ms is 10 times shorter interval than ulTaskNotifyTake 1 sec timeout...

you are right, we found it, the int pin is our old daughter boards not connected with ESP32 in our side. thank you. we fixed.