ESP32-S3 esp_phy_ble_tx and esp_phy_ble_rx (IDFGH-12108)

jbiemar commented 8 months ago

Answers checklist.

[X] I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
[X] I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
[X] I have searched the issue tracker for a similar issue and not found a similar issue.

IDF version.

v5.1.1 and v5.1.2 and v5.2-rc1

Espressif SoC revision.

ESP32-S3

Operating System used.

Linux

How did you build your project?

Command line with idf.py

If you are using Windows, please specify command line type.

None

Development Kit.

Custom Board

Power Supply used.

External 3.3V

What is the expected behavior?

We are designing a product centered on the ESP32 chip. For the certification tests, we use the certification APIs from file esp_phy_cert_test.h from component esp_phy.

WiFi TX and RX commands are working but I haven't any good result with BLE commands.

What is the actual behavior?

I receive in the struct:

typedef struct {
    uint32_t phy_rx_correct_count;                                     2
    int phy_rx_rssi;                                                               0
    uint32_t phy_rx_total_count;                                         0
    uint32_t phy_rx_result_flag;                                           2
} esp_phy_rx_result_t;

The phy_rx_result_flag seems correct but not rx count.

Steps to reproduce.

I do:

esp_phy_test_start_stop(3); on device A
esp_phy_ble_rx(1, 0x71764129, 0) on device A
esp_phy_test_start_stop(3); on device B
esp_phy_ble_tx(8, 1, 37, 0, 0x71764129, 0, 0) on device B
wait 20 seconds
esp_phy_test_start_stop(0); on device B
esp_phy_test_start_stop(0); on device A
esp_phy_get_rx_result on device A

Debug Logs.

Device A after RX:
I (121801) phy: RW LE V9 RX PER

Device A after cmdstop
I (152071) phy: rx_num: 0 rx_rssi: 0

Device A after get_result
I (153801) cmd_phy: Desired: 2, Correct: 0, RSSI: 0, flag: 2

Device B TX:
I (20591) phy: ble_tx:pwr=8,chan=1,len=37,type=2,syncw=0x71764129,rate=0,txnum=0

Device B cmdstop:
I (60441) phy: TX done! f904

Both device boot
> ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0xb (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3810,len:0x178c
load:0x403c9700,len:0x4
load:0x403c9704,len:0xcc8
load:0x403cc700,len:0x2e60
entry 0x403c9924
I (27) boot: ESP-IDF v5.2-rc1 2nd stage bootloader
I (27) boot: compile time Feb 12 2024 09:45:33
I (27) boot: Multicore bootloader
I (30) boot: chip revision: v0.1
I (34) boot.esp32s3: Boot SPI Speed : 80MHz
I (39) boot.esp32s3: SPI Mode       : DIO
I (43) boot.esp32s3: SPI Flash Size : 2MB
I (48) boot: Enabling RNG early entropy source...
I (54) boot: Partition Table:
I (57) boot: ## Label            Usage          Type ST Offset   Length
I (64) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (72) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (79) boot:  2 factory          factory app      00 00 00010000 00100000
I (87) boot: End of partition table
I (91) esp_image: segment 0: paddr=00010020 vaddr=3c040020 size=122f0h ( 74480) map
I (113) esp_image: segment 1: paddr=00022318 vaddr=3fc94b00 size=035c4h ( 13764) load
I (116) esp_image: segment 2: paddr=000258e4 vaddr=40374000 size=0a734h ( 42804) load
I (128) esp_image: segment 3: paddr=00030020 vaddr=42000020 size=3884ch (231500) map
I (170) esp_image: segment 4: paddr=00068874 vaddr=4037e734 size=06318h ( 25368) load
I (183) boot: Loaded app from partition at offset 0x10000
I (183) boot: Disabling RNG early entropy source...
I (195) cpu_start: Multicore app
V (195) mmap: after coalescing, 1 regions are left
D (195) cpu_start: Pro cpu up
D (195) cpu_start: Starting app cpu, entry point is 0x4037536c
D (0) cpu_start: App cpu up
V CACHE_ERR: illegal error intr clr & ena mask is: 0x3f
0x1fCHEDER2:9)cork: RT access er coribintronclr & ena m6ask
V CACHE_ERR: illegal error intr clr & ena mask is: 0x3f
V CACHE_ERR: core 0 access error intr clr & ena mask is: 0x1f
I (227) cpu_start: Pro cpu start user code
I (230) cpu_start: cpu freq: 240000000 Hz
I (235) cpu_start: Application information:
I (240) cpu_start: Project name:     cert_test
I (245) cpu_start: App version:      TEST_RF_4.0.0-dirty
I (251) cpu_start: Compile time:     Feb 12 2024 09:45:01
I (257) cpu_start: ELF file SHA256:  662aae548d2a3bad...
I (263) cpu_start: ESP-IDF:          v5.2-rc1
I (268) cpu_start: Min chip rev:     v0.0
I (273) cpu_start: Max chip rev:     v0.99
I (278) cpu_start: Chip rev:         v0.1
V (282) memory_layout: reserved range is 0x3c0522d0 - 0x3c0522f8
D (288) memory_layout: Checking 6 reserved memory ranges:
D (294) memory_layout: Reserved memory range 0x3fc84000 - 0x3fc94b00
D (300) memory_layout: Reserved memory range 0x3fc94b00 - 0x3fca31c0
D (307) memory_layout: Reserved memory range 0x3fceee34 - 0x3fcf0000
D (313) memory_layout: Reserved memory range 0x40374000 - 0x40384b00
D (320) memory_layout: Reserved memory range 0x600fe000 - 0x600fe010
D (326) memory_layout: Reserved memory range 0x600fffe8 - 0x60100000
D (332) memory_layout: Building list of available memory regions:
V (339) memory_layout: Examining memory region 0x3fc88000 - 0x3fc90000
V (345) memory_layout: Region 0x3fc88000 - 0x3fc90000 inside of reserved 0x3fc84000 - 0x3fc94b00
V (354) memory_layout: Examining memory region 0x3fc90000 - 0x3fca0000
V (361) memory_layout: Start of region 0x3fc90000 - 0x3fca0000 overlaps reserved 0x3fc84000 - 0x3fc94b00
V (370) memory_layout: Region 0x3fc94b00 - 0x3fca0000 inside of reserved 0x3fc94b00 - 0x3fca31c0
V (379) memory_layout: Examining memory region 0x3fca0000 - 0x3fcb0000
V (386) memory_layout: Start of region 0x3fca0000 - 0x3fcb0000 overlaps reserved 0x3fc94b00 - 0x3fca31c0
D (395) memory_layout: Available memory region 0x3fca31c0 - 0x3fcb0000
V (402) memory_layout: Examining memory region 0x3fcb0000 - 0x3fcc0000
D (408) memory_layout: Available memory region 0x3fcb0000 - 0x3fcc0000
V (415) memory_layout: Examining memory region 0x3fcc0000 - 0x3fcd0000
D (421) memory_layout: Available memory region 0x3fcc0000 - 0x3fcd0000
V (428) memory_layout: Examining memory region 0x3fcd0000 - 0x3fce0000
D (435) memory_layout: Available memory region 0x3fcd0000 - 0x3fce0000
V (441) memory_layout: Examining memory region 0x3fce0000 - 0x3fce9710
D (448) memory_layout: Available memory region 0x3fce0000 - 0x3fce9710
V (454) memory_layout: Examining memory region 0x3fce9710 - 0x3fcf0000
V (461) memory_layout: End of region 0x3fce9710 - 0x3fcf0000 overlaps reserved 0x3fceee34 - 0x3fcf0000
D (470) memory_layout: Available memory region 0x3fce9710 - 0x3fceee34
V (477) memory_layout: Examining memory region 0x3fcf0000 - 0x3fcf8000
D (484) memory_layout: Available memory region 0x3fcf0000 - 0x3fcf8000
V (490) memory_layout: Examining memory region 0x600fe000 - 0x60100000
V (497) memory_layout: Start of region 0x600fe000 - 0x60100000 overlaps reserved 0x600fe000 - 0x600fe010
V (506) memory_layout: End of region 0x600fe010 - 0x60100000 overlaps reserved 0x600fffe8 - 0x60100000
D (516) memory_layout: Available memory region 0x600fe010 - 0x600fffe8
I (522) heap_init: Initializing. RAM available for dynamic allocation:
D (530) heap_init: New heap initialised at 0x3fca31c0
I (535) heap_init: At 3FCA31C0 len 00046550 (281 KiB): RAM
I (541) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
D (547) heap_init: New heap initialised at 0x3fcf0000
I (552) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
D (558) heap_init: New heap initialised at 0x600fe010
I (563) heap_init: At 600FE010 len 00001FD8 (7 KiB): RTCRAM
V (570) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (576) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (584) intr_alloc: Connected src 39 to int 2 (cpu 0)
V (590) memspi: raw_chip_id: 174020

V (593) memspi: chip_id: 204017

V (596) memspi: raw_chip_id: 174020

V (600) memspi: chip_id: 204017

D (603) spi_flash: trying chip: issi
D (607) spi_flash: trying chip: gd
D (611) spi_flash: trying chip: mxic
D (614) spi_flash: trying chip: winbond
D (618) spi_flash: trying chip: boya
D (622) spi_flash: trying chip: th
D (625) spi_flash: trying chip: mxic (opi)
D (629) spi_flash: trying chip: generic
I (633) spi_flash: detected chip: generic
I (638) spi_flash: flash io: dio
W (642) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
D (655) cpu_start: calling init function: 0x420155d8
D (660) cpu_start: calling init function: 0x42015598
D (665) cpu_start: calling init function: 0x42013aac
D (670) cpu_start: calling init function: 0x42010ec4
W (675) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h`
D (686) cpu_start: calling init function: 0x4037ae50
D (691) cpu_start: calling init function: 0x42001f1c
D (696) cpu_start: calling init function: 0x42007080 on core: 0
V (702) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (708) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xC02
D (716) intr_alloc: Connected src 59 to int 3 (cpu 0)
D (721) cpu_start: calling init function: 0x42004ab0 on core: 0
I (728) sleep: Configure to isolate all GPIO pins in sleep state
I (734) sleep: Enable automatic switching of GPIO sleep configuration
D (741) cpu_start: calling init function: 0x42002f28 on core: 0
V (747) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (754) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (762) intr_alloc: Connected src 79 to int 9 (cpu 0)
D (767) app_start: Starting scheduler on CPU0
V (771) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (771) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x402
D (771) intr_alloc: Connected src 57 to int 12 (cpu 0)
V (771) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (781) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x40E
D (781) intr_alloc: Connected src 80 to int 2 (cpu 1)
D (791) app_start: Starting scheduler on CPU1
V (791) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (801) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x402
D (811) intr_alloc: Connected src 58 to int 3 (cpu 1)
I (771) main_task: Started on CPU0
D (821) heap_init: New heap initialised at 0x3fce9710
I (821) main_task: Calling app_main()
V (861) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (861) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (871) intr_alloc: Connected src 43 to int 13 (cpu 0)
V (1001) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (1001) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (1011) intr_alloc: Connected src 29 to int 17 (cpu 0)
I (3131) CONSOLE: Starting Console
V (3141) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (3141) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (3141) intr_alloc: Connected src 27 to int 18 (cpu 0)
I (3221) phy: rftest_init  start
D (3231) temperature_sensor: range changed, change to index 2
I (3251) phy: phy_version: 620, ec7ec30, Sep  5 2023, 13:49:13
I (3251) phy: libbtbb version: 2f6ef6d, Sep  5 2023, 13:49:33
I (3251) phy: LE autotest version: 40b80c1, Sep  5 2023, 13:49:37
I (3261) phy: mac_addr:7c:df:a1:e6:b9:c4
I (3261) phy: *RFTestBIN 111 ver 0

More Information.

No response

jbiemar commented 8 months ago

Resolved by Espressif:

I see customer is using channel 1. Have they tried other channels, e.g. 39? Channel 39 is one of the advertising channels, which allows transmit/receive advertising packets without a connection. I doubt you can transmit/receive packets without making a connection on data channels.

esp-zhp commented 7 months ago

@jbiemar I recently fixed an issue in the Direct Test Mode (DTM) where the count of received packets might be incorrect, potentially missing one under certain circumstances. I have already fixed this problem, but it hasn't been synchronized to GitHub yet. Is the issue you encountered related to this? commit will coming master eb92ea3461fda4b38a893791b1f601932a88b0ed v5.2 d0e94733f042afe15f299c35b6c8b2d099cc6a78 v5.1 a95d4807809b3ba1c17d3cb5143e0f114dbd487d v5.0 50ef8650ac3512eafe2605a16e154badae0e0482 v4.4 6b57f04cc819d4b426a118f5ec9b62645798cad4

espressif / esp-idf