Closed xiaguangbo closed 7 months ago
@xiaguangbo Hi~
SOC_SPI_HD_BOTH_INOUT_SUPPORTED
is really not supported for chips after esp32s2, it not a BUG but HW design changes.
But is not means these chips don't support half duplex, as error log reported:
SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.
It just a small changes that you need split tx and rx to independent transactions, ensure one transaction have only one direction. I don't know how rust implement 3-wire HD mode, but for esp-idf, can refer to test test_spi_sio.c
.
For the modification mentioned in https://github.com/esp-rs/esp-idf-hal/issues/401, it just work by accident, if txleng != rxleng, it not work as design.
@wanckl
I don't know what that means both MOSI and MISO phases are enabled
. phases enabled
meansCPHA = 1
? or tx and rx are enabled?
I don't understand this code. .embuild/espressif/esp-idf/v5.1.3/components/driver/spi/gpspi/spi_master.c L790:
#if !SOC_SPI_HD_BOTH_INOUT_SUPPORTED
//On these chips, HW doesn't support using both TX and RX phases when in halfduplex mode
SPI_CHECK(!is_half_duplex || !tx_enabled || !rx_enabled, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", ESP_ERR_INVALID_ARG);
SPI_CHECK(!is_half_duplex || !trans_desc->length || !trans_desc->rxlength, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", ESP_ERR_INVALID_ARG);
#endif
vscode prompt:
#define SPI_CHECK(a,str,ret_val) ESP_RETURN_ON_FALSE_ISR(a, ret_val, SPI_TAG, str)
扩展到:
do { if ((!(!is_half_duplex || !tx_enabled || !rx_enabled))) { ESP_EARLY_LOGE(SPI_TAG, "%s(%d): " "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", __FUNCTION__, 792); return 0x102; } } while(0)
#define SPI_CHECK(a,str,ret_val) ESP_RETURN_ON_FALSE_ISR(a, ret_val, SPI_TAG, str)
扩展到:
do { if ((!(!is_half_duplex || !trans_desc->length || !trans_desc->rxlength))) { ESP_EARLY_LOGE(SPI_TAG, "%s(%d): " "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", __FUNCTION__, 793); return 0x102; } } while(0)
@xiaguangbo ,,Sorry for confusing you,,
The code block you mentioned is a check, it is a hardware limitation
phases enabled
not means CPHA
half duplex means only one direction at a moment, then
both MOSI and MISO phases are enabled
This limitation is: in one transaction constructed in spi_transaction_t
, can only contain tx OR rx, if you need one TX followed by one RX, you need construct 2 spi_transaction_t
then start them independently
@wanckl
Problem is found ! It's a library function parameter problem.
/home/xiaguangbo/.cargo/registry/src/index.crates.io-6f17d22bba15001f/esp-idf-hal-0.43.1/src/spi.rs L1610
:
fn spi_read_transactions(
words: &mut [u8],
chunk_size: usize,
) -> impl Iterator<Item = spi_transaction_t> + '_ {
words.chunks_mut(chunk_size).map(|chunk| {
spi_create_transaction(
chunk.as_mut_ptr(),
core::ptr::null(),
chunk.len(), // problem is here. changed to 0
chunk.len(),
)
})
}
...
fn spi_create_transaction(
read: *mut u8,
write: *const u8,
transaction_length: usize,
rx_length: usize,
) -> spi_transaction_t {
spi_transaction_t {
flags: 0,
__bindgen_anon_1: spi_transaction_t__bindgen_ty_1 {
tx_buffer: write as *const _,
},
__bindgen_anon_2: spi_transaction_t__bindgen_ty_2 {
rx_buffer: read as *mut _,
},
length: (transaction_length * 8) as _,
rxlength: (rx_length * 8) as _,
..Default::default()
}
}
changed, cargo clean
cargo run
Answers checklist.
IDF version.
v5.1.3
Espressif SoC revision.
esp32c2 v1.0
Operating System used.
Linux
How did you build your project?
VS Code IDE
If you are using Windows, please specify command line type.
None
Development Kit.
nodemcu-esp32-c2
Power Supply used.
USB
What is the expected behavior?
use SPI Hafl3Wire
What is the actual behavior?
if not fix, can report some err https://github.com/esp-rs/esp-idf-hal/issues/401
Steps to reproduce.
https://github.com/esp-rs/esp-idf-hal/issues/401
Debug Logs.