KJ7LNW
commented
4 months ago As a proof of concept, this is one way to prevent the hang, by waiting only while the SCL line is low.
To prevent the spinning on hw->scl_sp_conf.scl_rst_slv_en I had to modify a chip specific header (esp32c6 in my case) and move while (hw->scl_sp_conf.scl_rst_slv_en) outside the low level function. Thus, adding something like a nowait parameter to i2c_ll_master_clr_bus() across chip implementations could be a solution.
With the diff below I can no longer hang the bus. You know the code best, so maybe there is an even better way to solve this:
diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c
index 4ee7c2b409..ef56bb01c5 100644
--- a/components/esp_driver_i2c/i2c_master.c
+++ b/components/esp_driver_i2c/i2c_master.c
@@ -75,6 +75,15 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
#else
i2c_hal_context_t *hal = &handle->hal;
i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT);
+
+ // It would be a good idea to add timout logic here and return an error,
+ // so the program can proceed without hanging if SCL is stuck low:
+ i2c_dev_t *hw = hal->dev;
+ while (hw->scl_sp_conf.scl_rst_slv_en && !gpio_get_level(handle->scl_num));
+ hw->ctr.conf_upgate = 1;
+
+ // Log if it would have hung, this is only for debug:
+ if (hw->scl_sp_conf.scl_rst_slv_en)
+ ESP_LOGE(TAG, "********************* I2C transaction would have hung!");
+
#endif
return ESP_OK;
}
diff --git a/components/hal/esp32c6/include/hal/i2c_ll.h b/components/hal/esp32c6/include/hal/i2c_ll.h
index 5d0ce895d3..340c4f8496 100644
--- a/components/hal/esp32c6/include/hal/i2c_ll.h
+++ b/components/hal/esp32c6/include/hal/i2c_ll.h
@@ -764,8 +764,8 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
- while (hw->scl_sp_conf.scl_rst_slv_en);
- hw->ctr.conf_upgate = 1;
}
/**
mythbuster5
AxelLin
eriksl
Hi @mythbuster5,
Thank you for your recent commits that help with I2C stability. At this point the only way that I can lock up/crash the chip (in a way that it cannot do error handling) is by randomly grounding the SCL line by hand with a pushbutton.
Eventually I can get it to hang with this WDT warning/trace:
Which causes it to spin here:
https://github.com/espressif/esp-idf/blob/636ff35b52f10e1a804a3760a5bd94e68f4b1b71/components/hal/esp32c6/include/hal/i2c_ll.h#L767
Note that pushing the reset button always "fixes" it and communication resumes after the reset.
Question
Based on the comment at the top of the function, perhaps nothing else that can be done to prevent this... but before I acquiesce to this limitation, I have a question:Is there a way to know if the 9x SCL pulses been sent by the hardware have completed, so that it can stop spinning and return control to the program, even if the bus really is locked up?
For example, can we just read the GPIO line level and return from the spinning
whileloop if the line is high?Here is the entire function for your reference:
https://github.com/espressif/esp-idf/blob/636ff35b52f10e1a804a3760a5bd94e68f4b1b71/components/hal/esp32c6/include/hal/i2c_ll.h#L749-L769