ESP32 - GPIO27 default state FUN_IE (IDFGH-12702)

[nkaaf]

Answers checklist.

• [X] I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• [X] I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• [X] I have searched the issue tracker for a similar issue and not found a similar issue.

IDF version.

v5.2.1

Espressif SoC revision.

ESP32-D0WDQ6 (revision v1.0)

Operating System used.

macOS

How did you build your project?

CLion IDE

If you are using Windows, please specify command line type.

None

Development Kit.

Dev Kit with ESP32-WROOM-32

Power Supply used.

USB

What is the expected behavior?

According to the Technical Reference Manual (5.1), the GPIO27 pin should be reset state '0', meaning 'input disabled'.

Information retrieved from page 60 'Table 4­3. IO_MUX Pad Summary'

What is the actual behavior?

If I dump the GPIO configuration of the GPIO27 pin, right at the beginning, the dump shows, that the input is enabled. This incorrect behavior only appears on GPIO27.

Steps to reproduce.

Code 1 (ESP-IDF GPIO):

#include <esp_log.h>
#include <freertos/FreeRTOS.h>
#include <freertos/task.h>
#include <driver/gpio.h>

void app_main()
{
  gpio_dump_io_configuration(stdout, 1ULL << 27);
  while (true)
  {
    vTaskDelay(5000 / portTICK_PERIOD_MS);
  }
}

Code 2 (Directly reading the register):

#include <esp_log.h>
#include <freertos/FreeRTOS.h>
#include <freertos/task.h>

void app_main()
{
  const int enable = (*(uint32_t*)0x3FF4902C & 0x200) >> 9;
  ESP_LOGI("GPIO27 FUN_IE", "Input enabled: %d", enable);

  while (true)
  {
    vTaskDelay(5000 / portTICK_PERIOD_MS);
  }
}

Debug Logs.

Code1:

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:7172
load:0x40078000,len:15540
load:0x40080400,len:4
ho 8 tail 4 room 4
load:0x40080404,len:3904
entry 0x40080640
I (31) boot: ESP-IDF v5.2.1 2nd stage bootloader
I (31) boot: compile time Apr 25 2024 07:26:35
I (31) boot: Multicore bootloader
I (35) boot: chip revision: v1.0
I (39) boot.esp32: SPI Speed      : 40MHz
I (44) boot.esp32: SPI Mode       : DIO
I (48) boot.esp32: SPI Flash Size : 2MB
I (53) boot: Enabling RNG early entropy source...
I (58) boot: Partition Table:
I (62) boot: ## Label            Usage          Type ST Offset   Length
I (69) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (76) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (84) boot:  2 factory          factory app      00 00 00010000 00100000
I (91) boot: End of partition table
I (96) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=099ach ( 39340) map
I (118) esp_image: segment 1: paddr=000199d4 vaddr=3ffb0000 size=0222ch (  8748) load
I (121) esp_image: segment 2: paddr=0001bc08 vaddr=40080000 size=04410h ( 17424) load
I (130) esp_image: segment 3: paddr=00020020 vaddr=400d0020 size=13918h ( 80152) map
I (159) esp_image: segment 4: paddr=00033940 vaddr=40084410 size=0834ch ( 33612) load
I (179) boot: Loaded app from partition at offset 0x10000
I (179) boot: Disabling RNG early entropy source...
I (191) cpu_start: Multicore app
I (199) cpu_start: Pro cpu start user code
I (199) cpu_start: cpu freq: 160000000 Hz
I (199) cpu_start: Application information:
I (202) cpu_start: Project name:     IO
I (207) cpu_start: App version:      1.0.0
I (212) cpu_start: Compile time:     Apr 25 2024 07:26:30
I (218) cpu_start: ELF file SHA256:  973c1a5bb...
I (223) cpu_start: ESP-IDF:          v5.2.1
I (228) cpu_start: Min chip rev:     v0.0
I (233) cpu_start: Max chip rev:     v3.99 
I (238) cpu_start: Chip rev:         v1.0
I (243) heap_init: Initializing. RAM available for dynamic allocation:
I (250) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (256) heap_init: At 3FFB2AF0 len 0002D510 (181 KiB): DRAM
I (262) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (268) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (275) heap_init: At 4008C75C len 000138A4 (78 KiB): IRAM
I (282) spi_flash: detected chip: generic
I (285) spi_flash: flash io: dio
W (289) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (303) main_task: Started on CPU0
I (313) main_task: Calling app_main()
================IO DUMP Start================
IO[27] -
  Pullup: 0, Pulldown: 0, DriveCap: 2
  InputEn: 1, OutputEn: 0, OpenDrain: 0
  FuncSel: 0 (IOMUX)
  SleepSelEn: 0

=================IO DUMP End==================

Code 2:

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:7172
load:0x40078000,len:15540
load:0x40080400,len:4
ho 8 tail 4 room 4
load:0x40080404,len:3904
entry 0x40080640
I (31) boot: ESP-IDF v5.2.1 2nd stage bootloader
I (31) boot: compile time Apr 25 2024 07:26:35
I (31) boot: Multicore bootloader
I (35) boot: chip revision: v1.0
I (39) boot.esp32: SPI Speed      : 40MHz
I (44) boot.esp32: SPI Mode       : DIO
I (48) boot.esp32: SPI Flash Size : 2MB
I (53) boot: Enabling RNG early entropy source...
I (58) boot: Partition Table:
I (62) boot: ## Label            Usage          Type ST Offset   Length
I (69) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (76) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (84) boot:  2 factory          factory app      00 00 00010000 00100000
I (91) boot: End of partition table
I (96) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=0955ch ( 38236) map
I (117) esp_image: segment 1: paddr=00019584 vaddr=3ffb0000 size=0220ch (  8716) load
I (121) esp_image: segment 2: paddr=0001b798 vaddr=40080000 size=04880h ( 18560) load
I (130) esp_image: segment 3: paddr=00020020 vaddr=400d0020 size=133f0h ( 78832) map
I (159) esp_image: segment 4: paddr=00033418 vaddr=40084880 size=07e9ch ( 32412) load
I (178) boot: Loaded app from partition at offset 0x10000
I (178) boot: Disabling RNG early entropy source...
I (189) cpu_start: Multicore app
I (198) cpu_start: Pro cpu start user code
I (198) cpu_start: cpu freq: 160000000 Hz
I (198) cpu_start: Application information:
I (201) cpu_start: Project name:     IO
I (206) cpu_start: App version:      1.0.0
I (211) cpu_start: Compile time:     Apr 25 2024 07:26:30
I (217) cpu_start: ELF file SHA256:  1af5ecca2...
I (222) cpu_start: ESP-IDF:          v5.2.1
I (227) cpu_start: Min chip rev:     v0.0
I (232) cpu_start: Max chip rev:     v3.99 
I (236) cpu_start: Chip rev:         v1.0
I (241) heap_init: Initializing. RAM available for dynamic allocation:
I (248) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM[0
I (254) heap_init: At 3FFB2AD0 len 0002D530 (181 KiB): DRAM
I (261) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (267) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (273) heap_init: At 4008C71C len 000138E4 (78 KiB): IRAM
I (281) spi_flash: detected chip: generic
I (284) spi_flash: flash io: dio
W (288) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (302) main_task: Started on CPU0
I (312) main_task: Calling app_main()
I (312) GPIO27 FUN_IE: Input enabled: 1

### More Information.

_No response_

[songruo]

As we explained in your other issue, you shouldn't be relying on the default values that were documented in the TRM. We will add a note to the programming guide to let the users aware of it.