Open MR-VENOM opened 1 month ago
one workaround is, .clk_cfg = LEDC_AUTO_CLK
-> .clk_cfg = LEDC_USE_XTAL_CLK
Hi @MR-VENOM, the key problem is that all timers are sharing one clock source. While timer 0 wants a 4kHz signal, this can be achieved with either APB or XTAL clock sources, timer 1 wants a 50Hz signal, this can only be achieved with XTAL clock. When you first configured for timer 0 with LEDC_AUTO_CLK
, the driver selected the clock source to be APB, and that's the reason why later you configure for timer 1, the driver notices the conflict between APB and XTAL.
In your situation, I think the users should be very clear on the clock source choice, and avoid using LEDC_AUTO_CLK
.
We will consider provide a helper API, by giving the timer configuration, returns all the feasible clock sources for such a timer.
Hi @MR-VENOM, the key problem is that all timers are sharing one clock source. While timer 0 wants a 4kHz signal, this can be achieved with either APB or XTAL clock sources, timer 1 wants a 50Hz signal, this can only be achieved with XTAL clock. When you first configured for timer 0 with
LEDC_AUTO_CLK
, the driver selected the clock source to be APB, and that's the reason why later you configure for timer 1, the driver notices the conflict between APB and XTAL.In your situation, I think the users should be very clear on the clock source choice, and avoid using
LEDC_AUTO_CLK
.We will consider provide a helper API, by giving the timer configuration, returns all the feasible clock sources for such a timer.
But the documentation says the LEDC AUTO CLOCK will select the clk automatically with the given frequency and resolution. And one thing I notices is when I give 13bit the error does not happen.
Yes, LEDC_AUTO_CLK works fine if you are only configuring one timer. As I explained in the previous thread, the problem is two timers are configured one after another. The first one has no way to know the next timer being configured can only use XTAL as the clock source.
With 13-bit resolution, the error does not happen is because, in such case, even 50Hz timer can also use APB as the clock source.
Answers checklist.
IDF version.
v5.2.1
Espressif SoC revision.
ESP32-S3 (QFN56) (revision v0.1)
Operating System used.
Linux
How did you build your project?
Command line with idf.py
If you are using Windows, please specify command line type.
None
Development Kit.
Custom board
Power Supply used.
USB
What is the expected behavior?
Trying to create 2 LEDC channel with diffrent frequency 50hz and 4khz. On timer 0 and timer 1.
What is the actual behavior?
ESP crashes with the bellow backtrace.
Steps to reproduce.
Debug Logs.
More Information.
No response