Open ftab opened 1 month ago
Just spotted in esp-idf/components/esp_hw_support/port/esp32p4/esp_clk_tree.c:
// case SOC_MOD_CLK_APLL: TODO: IDF-8884
That explains the APLL not working. How can I stay apprised of the status of IDF-8884? Any word on when it's planned to be implemented?
Same issue here - trying to work with TDM16. It is partially working at 22050Hz, but not properly.
Hi @ftab @DatanoiseTV , thanks for your reporting! I2S on P4 only has XTAL and APLL two internal clock sources (the PLL clock source is not supported). As APLL support has not merged yet, I2S can only use XTAL clock for now, which is up to 40MHz.
See the similar issue #14448. And the APLL support patch is uploaded there for testing.
Hi @ftab @DatanoiseTV , thanks for your reporting!
I2S on P4 only has XTAL and APLL two internal clock sources (the PLL clock source is not supported). As APLL support has not merged yet, I2S can only use XTAL clock for now, which is up to 40MHz.
See the similar issue #14448. And the APLL support patch is uploaded there for testing.
I can confirm the patch works. Thanks!
FYI, APLL has been supported on the master in this commit
You can rebase on the master to use APLL as well
Answers checklist.
IDF version.
v5.3
Espressif SoC revision.
ESP32-P4 v0.1
Operating System used.
Linux
How did you build your project?
Command line with idf.py
If you are using Windows, please specify command line type.
None
Development Kit.
ESP32-P4 EV board
Power Supply used.
USB
What is the expected behavior?
Create I2S clock from APLL
What is the actual behavior?
fails to initialize clock
Steps to reproduce.
Using ESP-ADF i2s_stream in a simple audio pipeline to read /usb/test.mp3, split from 2 to 8 channels with our audio DSP code, then play to a PCM1681 (8ch DAC) over I2S TDM
Here is the snippet of code where the i2s stream is set up
Debug Logs.
More Information.
Using my fork of ESP-ADF that hacks some stuff out to work on the P4 as ESP-ADF v2.7 is not released yet: https://github.com/radiosound-com/esp-adf/tree/radiosound-modded-v2.6-141-g218cf614-idf-v5.3-modded
When I change I2S_CLK_SRC_APLL to I2S_CLK_SRC_DEFAULT, i2s does initialize, but MCLK is running at 20mhz (expected: 44,100 x 768 = 33,868,800) and WS runs at 26khz instead of 44.1khz