ESP32-S3: RMT RX group clock for 420uS (IDFGH-13631)

[dpnebert]

Answers checklist.

• [X] I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• [X] I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• [X] I have searched the issue tracker for a similar issue and not found a similar issue.

General issue report

This is a 'ESP32-S3' chip with 2 CPU cores, WiFi/BLE, silicon revision v0.2, 8MB external flash

The only other issue I found about RMT RX was very helpful: https://github.com/espressif/esp-idf/issues/12753

The calculation I am working on is:

uint32_t filter_reg_value = ((uint64_t)group->resolution_hz * config->signal_range_min_ns) / 1000000000UL;

And reading through the source, I see that after that assignment, it does an error check:

ESP_RETURN_ON_FALSE_ISR(filter_reg_value <= RMT_LL_MAX_FILTER_VALUE, ESP_ERR_INVALID_ARG, TAG, "signal_range_min_ns too big");

And in "components/hal/esp32s3/include/hal/rmt_ll.h":

#define RMT_LL_MAX_FILTER_VALUE 255

So, 'filter_reg_value' can't be more than 255. And I'll need a group clock that after the above calculation, provides a 'filter_reg_value' between 1 and 255. Rewriting the formula:

group->resolution_hz = ( filter_reg_value * 1000000000UL) / range_min_ns

If: filter_reg_value = 1 range_min_ns = 420000 // 420uS

Then group->resolution_hz is 2380.952380952381 Hz

If: filter_reg_value = 255 range_min_ns = 420000 // 420uS

Then group->resolution_hz is 607142.8571428571 Hz

I found the RMT clock sources at: components/soc/esp32s3/include/soc/clk_tree_defs.h

Which listed:

typedef enum { RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /!< Select APB as the source clock / RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /!< Select RC_FAST as the source clock / RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /!< Select XTAL as the source clock / RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /!< Select APB as the default choice / } soc_periph_rmt_clk_src_t;

Which is nothing in the realm of my 500KHz clock I'd need to get 420uS. Am I going about this wrong? What am I missing?

[florentbr]

The maximum filter with the APB clock selected should be at 3.187us (255/80e6) and 31.87us with the RC fast clock (8Mhz).

[dpnebert]

@florentbr I understand there isn't anything to help me reach a filter_min_ns of 420,000 uS?

I was hoping for a 1MHz clock I guess.