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espressif / esp-idf

Espressif IoT Development Framework. Official development framework for Espressif SoCs.
Apache License 2.0
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SPI cs_ena_posttrans wrong range (IDFGH-765) #2441

Open michprev opened 6 years ago

michprev commented 6 years ago

https://github.com/espressif/esp-idf/blob/aaf12390eb14b95589acd98db5c268a2e56bb67e/components/driver/include/driver/spi_master.h#L72

cs_ena_posttrans sets SPI_HOLD_TIME 4 bit field in SPI_CTRL2_REG register. Because of hardware bug SPI_HOLD_TIME starts from 0 and not from 1 so the correct range is 0 - 15

See https://github.com/espressif/esp-idf/blob/7abed5fc9e0b652c1db85523a721f56050288d2e/components/driver/spi_master.c#L596-L600

Also I don't quite understand this comment //set it to 1 since we do need at least one clock of hold time in most cases

Isn't it up to user of the driver to decide that he needs delay on CS or not?

Alvin1Zhang commented 5 years ago

@michprev Thanks for reporting this.