ssymo84
commented
2 years ago I think is I2S clock issue and prescaler used also for ADC DMA.
In components/hal/adc_hal.c :
//ESP32 ADC uses the DMA through I2S. The I2S needs to be configured.
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
#define SAMPLE_BITS 16
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 2
#define ADC_LL_CLKM_DIV_B_DEFAULT 0
#define ADC_LL_CLKM_DIV_A_DEFAULT 1/**
* For esp32s2 and later chips
* - Set ADC digital controller clock division factor. The clock is divided from `APLL` or `APB` clock.
* Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1).
* - Enable clock and select clock source for ADC digital controller.
* For esp32, use I2S clock
*/
static void adc_hal_digi_sample_freq_config(adc_hal_context_t *hal, uint32_t freq)
{
#if !CONFIG_IDF_TARGET_ESP32
uint32_t interval = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / freq;
//set sample interval
adc_ll_digi_set_trigger_interval(interval);
//Here we set the clock divider factor to make the digital clock to 5M Hz
adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT);
adc_ll_digi_clk_sel(0); //use APB
#else
i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); /*!< Clock from PLL_D2_CLK(160M)*/
uint32_t bck = I2S_BASE_CLK / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_B_DEFAULT / ADC_LL_CLKM_DIV_A_DEFAULT) / 2 / freq;
i2s_ll_mclk_div_t clk = {
.mclk_div = ADC_LL_CLKM_DIV_NUM_DEFAULT,
.a = ADC_LL_CLKM_DIV_A_DEFAULT,
.b = ADC_LL_CLKM_DIV_B_DEFAULT,
};
i2s_ll_rx_set_clk(hal->dev, &clk);
i2s_ll_rx_set_bck_div_num(hal->dev, bck);
#endif
}If the setted sampling frequency is 10e3, the variable bck=160e6/(2+0)/2/10e3=4000 but the I2S_RX_BCK_DIV_NUM[5:0] is only 6 bit wide, so the maximum is 63.
I tried changing
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 256and the real sampling frequency slow down, the buffer isn't no more always overflowing and the channel sequence is correct.
But I don't know what the exact clock prescaler for which the code was designed for, documentation is not so clear...
dzanis
higaski
haukurhafsteins
We have the variables N, a, b and M that control the sampling frequency. This image does not take into account the number of channels being sampled and the bits in each sample. All these values are set in two registers:
The number ranges are:
20480Hz
N: 65 M: 10 a:48 b: 5
23456.0Hz
N: 94 M: 6 a:50 b:37
80000Hz (5khz signal as input)
NOTE: There were quite a few numbers to select from and not all worked.
N: 3 M: 42 a:63 b:61
409.60453125 KHz
N: 8 M: 4 a:58 b: 8
823984418
fiy-max
ScumCoder
Environment
Problem Description
I'm trying to do real-time sampling of 4 input signals using the onboard ADCs; as best I can tell, the ADC DMA mode should be a good way to do this, despite the lack of documentation.
So I copied the dma_read example and tweaked it to fit my use case. But as soon as I removed the time-consuming print statements, it was generating far more samples than it seemed like it was supposed to.
(Could this be related to #6691? I don't know the code well enough to guess...)
Expected Behavior
Since I've reduced the config values to
sample_freq_hz = 2000andconv_num_each_intr = 8, I would expect to be getting 16000 bytes per second.Actual Behavior
I'm getting around 865000 bytes per second.
Steps to reproduce
Here's my code (a slight modification of the dma_read example code - I've tweaked the parameters, removed the excess prints, infrequently logged the average number of bytes read, and stripped out the non-ESP32-specific code) https://gist.github.com/elidupree/cfdbff1b909eb8654f8b5ca38642e726
I simply put that code in the place of the dma_read main file, build and flash over USB to an unmodified WeMos D1 Mini ESP32; no extra wiring is needed.
Debug Logs