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espressif / openocd-esp32

OpenOCD branch with ESP32 JTAG support
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ESP32C3 openocd fail -- Hart is not halted! (OCD-420) #183

Closed jonsmirl closed 2 years ago

jonsmirl commented 2 years ago

I have been trying to get openocd functioning on the C3 for a couple of weeks now without success. Sometimes it will work for a little while and then it fails and nothing I do can revive it. So I built openocd-esp32 from source as of 10/22 to ensure I have the very latest version.

I am running nothing besides openocd from source and riscv32-esp-elf-gdb. The 'target remote :3333" command fails to execute. That is because openocd is failing to work properly.....

jonsmirl@ares:~/aosp/openocd-esp32$ ./src/openocd -f board/esp32c3-builtin.cfg Open On-Chip Debugger v0.10.0-esp32-20210902-15-g78ea2222 (2021-10-22-19:00) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Info : only one transport option; autoselect 'jtag' Warn : Transport "jtag" was already selected Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections Info : esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255 Info : clock speed 40000 kHz Info : JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0) Info : datacount=2 progbufsize=16 Info : Examined RISC-V core; found 1 harts Info : hart 0: XLEN=32, misa=0x40101104 Info : Listening on port 3333 for gdb connections Info : accepting 'gdb' connection on tcp/3333 Warn : No symbols for FreeRTOS! Error: Hart is not halted! Error: Failed to wait algorithm (-4)! Error: Algorithm run failed (-4)! Error: Failed to run flasher stub (-4)! Warn : Failed to get flash mappings (-4)! Error: Abstract command ended in error 'exception' (abstractcs=0x10001302) Error: Timed out after 5s waiting for busy to go low (abstractcs=0x10001302). Increase the timeout with riscv set_command_timeout_sec. Error: Failed to write stub section! Error: Failed to run flasher stub (-4)! Error: Abstract command ended in error 'exception' (abstractcs=0x10001302) Error: Timed out after 5s waiting for busy to go low (abstractcs=0x10001302). Increase the timeout with riscv set_command_timeout_sec. Error: Failed to write stub section! Error: Failed to run flasher stub (-4)! Error: Failed to probe flash, size 0 KB Error: auto_probe failed Error: Connect failed. Consider setting up a gdb-attach event for the target to prepare target for GDB connect, or use 'gdb_memory_map disable'. Error: attempted 'gdb' connection rejected

jonsmirl@ares:~/aosp/connectedhomeip/examples/lighting-app/esp32$ riscv32-esp-elf-gdb GNU gdb (crosstool-NG esp-2021r2) 9.2.90.20200913-git Copyright (C) 2020 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=x86_64-build_pc-linux-gnu --target=riscv32-esp-elf". Type "show configuration" for configuration details. For bug reporting instructions, please see: http://www.gnu.org/software/gdb/bugs/. Find the GDB manual and other documentation resources online at: http://www.gnu.org/software/gdb/documentation/.

For help, type "help". Type "apropos word" to search for commands related to "word". (gdb) set target :3333 Ambiguous set command "target :3333": target-async, target-charset, target-file-system-kind, target-wide-charset. (gdb) target remote :3333 Remote debugging using :3333 Ignoring packet error, continuing... warning: unrecognized item "timeout" in "qSupported" response Remote communication error. Target disconnected.: Connection reset by peer. (gdb) target remote :3333 Remote debugging using :3333 Ignoring packet error, continuing... warning: unrecognized item "timeout" in "qSupported" response Remote communication error. Target disconnected.: Connection reset by peer. (gdb) quit

jonsmirl commented 2 years ago

Open On-Chip Debugger v0.10.0-esp32-20210902-15-g78ea2222 (2021-10-22-19:00) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html User : 13 2 options.c:57 configuration_output_handler(): debug_level: 3 User : 14 2 options.c:57 configuration_output_handler(): Debug: 15 2 options.c:181 add_default_dirs(): bindir=/usr/local/bin Debug: 16 2 options.c:182 add_default_dirs(): pkgdatadir=/usr/local/share/openocd Debug: 17 2 options.c:183 add_default_dirs(): exepath=/home/jonsmirl/aosp/openocd-esp32/src Debug: 18 2 options.c:184 add_default_dirs(): bin2data=../share/openocd Debug: 19 2 configuration.c:42 add_script_search_dir(): adding /home/jonsmirl/.openocd Debug: 20 2 configuration.c:42 add_script_search_dir(): adding /home/jonsmirl/.espressif/tools/openocd-esp32/v0.10.0-esp32-20210902/openocd-esp32/share/openocd/scripts Debug: 21 2 configuration.c:42 add_script_search_dir(): adding /home/jonsmirl/aosp/openocd-esp32/src/../share/openocd/site Debug: 22 2 configuration.c:42 add_script_search_dir(): adding /home/jonsmirl/aosp/openocd-esp32/src/../share/openocd/scripts Debug: 23 2 configuration.c:97 find_file(): found /home/jonsmirl/.espressif/tools/openocd-esp32/v0.10.0-esp32-20210902/openocd-esp32/share/openocd/scripts/board/esp32c3-builtin.cfg Debug: 24 2 configuration.c:97 find_file(): found /home/jonsmirl/.espressif/tools/openocd-esp32/v0.10.0-esp32-20210902/openocd-esp32/share/openocd/scripts/interface/esp_usb_jtag.cfg Debug: 25 2 command.c:143 script_debug(): command - interface interface esp_usb_jtag Debug: 27 2 command.c:355 register_command_handler(): registering 'espusbjtag'... Debug: 28 2 command.c:355 register_command_handler(): registering 'espusbjtag'... Debug: 29 2 command.c:355 register_command_handler(): registering 'espusbjtag'... Debug: 30 2 command.c:355 register_command_handler(): registering 'espusbjtag'... Info : 31 2 transport.c:117 allow_transports(): only one transport option; autoselect 'jtag' Debug: 32 2 command.c:355 register_command_handler(): registering 'jtag_flush_queue_sleep'... Debug: 33 2 command.c:355 register_command_handler(): registering 'jtag_rclk'... Debug: 34 3 command.c:355 register_command_handler(): registering 'jtag_ntrst_delay'... Debug: 35 3 command.c:355 register_command_handler(): registering 'jtag_ntrst_assert_width'... Debug: 36 3 command.c:355 register_command_handler(): registering 'scan_chain'... Debug: 37 3 command.c:355 register_command_handler(): registering 'jtag_reset'... Debug: 38 3 command.c:355 register_command_handler(): registering 'runtest'... Debug: 39 3 command.c:355 register_command_handler(): registering 'irscan'... Debug: 40 3 command.c:355 register_command_handler(): registering 'verify_ircapture'... Debug: 41 3 command.c:355 register_command_handler(): registering 'verify_jtag'... Debug: 42 3 command.c:355 register_command_handler(): registering 'tms_sequence'... Debug: 43 3 command.c:355 register_command_handler(): registering 'wait_srst_deassert'... Debug: 44 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 45 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 46 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 47 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 48 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 49 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 50 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 51 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 52 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 53 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 54 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 55 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 56 3 command.c:355 register_command_handler(): registering 'jtag'... Debug: 57 3 command.c:355 register_command_handler(): registering 'svf'... Debug: 58 3 command.c:355 register_command_handler(): registering 'xsvf'... Debug: 59 3 command.c:143 script_debug(): command - adapter_khz adapter_khz 40000 Debug: 61 3 core.c:1704 jtag_config_khz(): handle jtag khz Debug: 62 3 core.c:1667 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 63 3 core.c:1667 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 64 3 configuration.c:97 find_file(): found /home/jonsmirl/.espressif/tools/openocd-esp32/v0.10.0-esp32-20210902/openocd-esp32/share/openocd/scripts/target/esp32c3.cfg Debug: 65 3 command.c:143 script_debug(): command - transport transport select jtag Warn : 66 3 transport.c:297 jim_transport_select(): Transport "jtag" was already selected Debug: 67 3 configuration.c:97 find_file(): found /home/jonsmirl/.espressif/tools/openocd-esp32/v0.10.0-esp32-20210902/openocd-esp32/share/openocd/scripts/target/esp_common.cfg Debug: 68 3 command.c:143 script_debug(): command - add_help_text add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock are optional Debug: 70 3 command.c:1127 help_add_command(): added 'program_esp' help text Debug: 71 3 command.c:143 script_debug(): command - add_usage_text add_usage_text program_esp [address] [verify] [reset] [exit] [compress] [restore_clock] Debug: 73 3 command.c:1153 help_add_command(): added 'program_esp' usage text Debug: 74 3 command.c:143 script_debug(): command - add_help_text add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project Debug: 76 3 command.c:1127 help_add_command(): added 'program_esp_bins' help text Debug: 77 3 command.c:143 script_debug(): command - add_usage_text add_usage_text program_esp_bins flasher_args.json [verify] [reset] [exit] [compress] [restore_clock] Debug: 79 3 command.c:1153 help_add_command(): added 'program_esp_bins' usage text Debug: 80 3 command.c:143 script_debug(): command - add_help_text add_help_text esp_get_mac Print MAC address of the chip. Use a format argument to return formatted MAC value Debug: 82 3 command.c:1127 help_add_command(): added 'esp_get_mac' help text Debug: 83 3 command.c:143 script_debug(): command - add_usage_text add_usage_text esp_get_mac [format] Debug: 85 3 command.c:1153 help_add_command(): added 'esp_get_mac' usage text Debug: 86 3 command.c:143 script_debug(): command - jtag jtag newtap esp32c3 cpu -irlen 5 -expected-id 0x00005c25 Debug: 87 3 tcl.c:566 jim_newtap_cmd(): Creating New Tap, Chip: esp32c3, Tap: cpu, Dotted: esp32c3.cpu, 4 params Debug: 88 3 tcl.c:591 jim_newtap_cmd(): Processing option: -irlen Debug: 89 3 tcl.c:591 jim_newtap_cmd(): Processing option: -expected-id Debug: 90 3 core.c:1368 jtag_tap_init(): Created Tap: esp32c3.cpu @ abs position 0, irlen 5, capture: 0x1 mask: 0x3 Debug: 91 3 command.c:143 script_debug(): command - target target create esp32c3 esp32c3 -chain-position esp32c3.cpu -rtos FreeRTOS Debug: 92 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 93 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 94 3 FreeRTOS.c:1225 FreeRTOS_create(): FreeRTOS_create Debug: 95 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 96 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 97 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 98 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 99 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 100 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 101 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 102 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 103 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 104 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 105 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 106 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 107 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 108 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 109 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 110 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 111 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 112 3 command.c:355 register_command_handler(): registering 'riscv'... Debug: 113 3 command.c:355 register_command_handler(): registering 'arm'... Debug: 114 3 command.c:355 register_command_handler(): registering 'arm'... Debug: 115 3 command.c:355 register_command_handler(): registering 'arm'... Debug: 116 3 command.c:355 register_command_handler(): registering 'arm'... Debug: 117 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 118 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 119 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 120 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 121 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 122 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 123 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 124 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 125 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 126 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 127 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 128 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 129 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 130 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 131 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 132 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 133 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 134 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 135 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 136 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 137 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 138 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 139 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 140 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 141 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 142 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 143 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 144 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 145 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 146 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 147 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 148 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 149 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 150 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 151 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 152 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 153 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 154 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 155 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 156 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 157 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 158 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 159 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 160 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 161 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 162 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 163 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 164 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 165 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 166 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 167 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 168 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 169 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 170 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 171 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 172 3 command.c:355 register_command_handler(): registering 'esp32c3'... Debug: 173 3 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -event reset-assert-post esp32c3_soc_reset Debug: 174 3 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -event halted esp32c3_wdt_disable Debug: 175 3 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -event examine-end

Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default

arm semihosting enable
arm semihosting_resexit enable

Debug: 176 3 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -event gdb-attach

'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map

halt
# by default mask interrupts while stepping
riscv maskisr steponly

Debug: 177 3 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -work-area-phys 0x40380000 -work-area-virt 0x40380000 -work-area-size 0x4000 -work-area-backup 1 Debug: 178 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 179 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 180 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 181 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 182 3 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -alt-work-area-phys 0x3FC84000 -alt-work-area-virt 0x3FC84000 -alt-work-area-size 0x20000 -alt-work-area-backup 1 Debug: 183 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 184 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 185 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 186 3 target.c:2012 target_free_all_working_areas_restore(): freeing all working areas Debug: 187 3 command.c:143 script_debug(): command - flash flash bank esp32c3.flash esp32c3 0x0 0 0 0 esp32c3 Debug: 189 3 command.c:376 register_command(): command 'esp' is already registered in '' context Debug: 190 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 191 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 192 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 193 3 command.c:355 register_command_handler(): registering 'esp'... Debug: 194 3 tcl.c:1156 handle_flash_bank_command(): 'esp32c3' driver usage field missing Debug: 195 3 command.c:143 script_debug(): command - flash flash bank esp32c3.irom esp32c3 0x0 0 0 0 esp32c3 Debug: 197 3 command.c:376 register_command(): command 'esp' is already registered in '' context Debug: 198 3 command.c:376 register_command(): command 'appimage_offset' is already registered in 'esp' context Debug: 199 3 command.c:376 register_command(): command 'compression' is already registered in 'esp' context Debug: 200 3 command.c:376 register_command(): command 'verify_bank_hash' is already registered in 'esp' context Debug: 201 3 command.c:376 register_command(): command 'flash_stub_clock_boost' is already registered in 'esp' context Debug: 202 3 tcl.c:1156 handle_flash_bank_command(): 'esp32c3' driver usage field missing Debug: 203 3 command.c:143 script_debug(): command - flash flash bank esp32c3.drom esp32c3 0x0 0 0 0 esp32c3 Debug: 205 3 command.c:376 register_command(): command 'esp' is already registered in '' context Debug: 206 4 command.c:376 register_command(): command 'appimage_offset' is already registered in 'esp' context Debug: 207 4 command.c:376 register_command(): command 'compression' is already registered in 'esp' context Debug: 208 4 command.c:376 register_command(): command 'verify_bank_hash' is already registered in 'esp' context Debug: 209 4 command.c:376 register_command(): command 'flash_stub_clock_boost' is already registered in 'esp' context Debug: 210 4 tcl.c:1156 handle_flash_bank_command(): 'esp32c3' driver usage field missing Debug: 211 4 command.c:143 script_debug(): command - riscv riscv set_reset_timeout_sec 2 Debug: 213 4 command.c:143 script_debug(): command - riscv riscv set_command_timeout_sec 5 Debug: 215 4 command.c:143 script_debug(): command - riscv riscv set_prefer_sba on Info : 217 4 server.c:310 add_service(): Listening on port 6666 for tcl connections Info : 218 4 server.c:310 add_service(): Listening on port 4444 for telnet connections Debug: 219 4 command.c:143 script_debug(): command - init init Debug: 221 4 command.c:143 script_debug(): command - target target init Debug: 223 4 command.c:143 script_debug(): command - target target names Debug: 224 4 command.c:143 script_debug(): command - esp32c3 esp32c3 cget -event gdb-flash-erase-start Debug: 225 4 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -event gdb-flash-erase-start reset init Debug: 226 4 command.c:143 script_debug(): command - esp32c3 esp32c3 cget -event gdb-flash-write-end Debug: 227 4 command.c:143 script_debug(): command - esp32c3 esp32c3 configure -event gdb-flash-write-end reset halt Debug: 228 4 command.c:143 script_debug(): command - esp32c3 esp32c3 cget -event gdb-attach Debug: 229 4 target.c:1450 handle_target_init_command(): Initializing targets... Debug: 230 4 esp32c3.c:155 esp32c3_init_target(): enter Debug: 231 5 semihosting_common.c:98 semihosting_common_init():
Debug: 232 5 command.c:355 register_command_handler(): registering 'target_request'... Debug: 233 5 command.c:355 register_command_handler(): registering 'trace'... Debug: 234 5 command.c:355 register_command_handler(): registering 'trace'... Debug: 235 5 command.c:355 register_command_handler(): registering 'fast_load_image'... Debug: 236 5 command.c:355 register_command_handler(): registering 'fast_load'... Debug: 237 5 command.c:355 register_command_handler(): registering 'profile'... Debug: 238 5 command.c:355 register_command_handler(): registering 'virt2phys'... Debug: 239 5 command.c:355 register_command_handler(): registering 'reg'... Debug: 240 5 command.c:355 register_command_handler(): registering 'poll'... Debug: 241 5 command.c:355 register_command_handler(): registering 'wait_halt'... Debug: 242 5 command.c:355 register_command_handler(): registering 'halt'... Debug: 243 5 command.c:355 register_command_handler(): registering 'resume'... Debug: 244 5 command.c:355 register_command_handler(): registering 'reset'... Debug: 245 5 command.c:355 register_command_handler(): registering 'soft_reset_halt'... Debug: 246 5 command.c:355 register_command_handler(): registering 'step'... Debug: 247 5 command.c:355 register_command_handler(): registering 'mdd'... Debug: 248 5 command.c:355 register_command_handler(): registering 'mdw'... Debug: 249 5 command.c:355 register_command_handler(): registering 'mdh'... Debug: 250 5 command.c:355 register_command_handler(): registering 'mdb'... Debug: 251 5 command.c:355 register_command_handler(): registering 'mwd'... Debug: 252 5 command.c:355 register_command_handler(): registering 'mww'... Debug: 253 5 command.c:355 register_command_handler(): registering 'mwh'... Debug: 254 5 command.c:355 register_command_handler(): registering 'mwb'... Debug: 255 5 command.c:355 register_command_handler(): registering 'bp'... Debug: 256 5 command.c:355 register_command_handler(): registering 'rbp'... Debug: 257 5 command.c:355 register_command_handler(): registering 'wp'... Debug: 258 5 command.c:355 register_command_handler(): registering 'rwp'... Debug: 259 5 command.c:355 register_command_handler(): registering 'load_image'... Debug: 260 5 command.c:355 register_command_handler(): registering 'dump_image'... Debug: 261 5 command.c:355 register_command_handler(): registering 'verify_image_checksum'... Debug: 262 5 command.c:355 register_command_handler(): registering 'verify_image'... Debug: 263 5 command.c:355 register_command_handler(): registering 'test_image'... Debug: 264 5 command.c:355 register_command_handler(): registering 'reset_nag'... Debug: 265 5 command.c:355 register_command_handler(): registering 'ps'... Debug: 266 5 command.c:355 register_command_handler(): registering 'test_mem_access'... Debug: 267 12 libusb1_common.c:303 jtag_libusb_choose_interface(): usb ep out 02 Debug: 268 12 libusb1_common.c:303 jtag_libusb_choose_interface(): usb ep in 83 Debug: 269 12 libusb1_common.c:312 jtag_libusb_choose_interface(): Claiming interface 2 Info : 270 12 esp_usb_jtag.c:719 esp_usb_jtag_init(): esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255 Debug: 271 12 core.c:1667 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 272 12 core.c:1671 adapter_khz_to_speed(): have interface set up Debug: 273 12 esp_usb_jtag.c:763 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1 Debug: 274 12 esp_usb_jtag.c:782 esp_usb_jtag_speed(): esp_usb_jtag: setting divisor 1 Debug: 275 13 core.c:1667 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 276 13 core.c:1671 adapter_khz_to_speed(): have interface set up Debug: 277 13 esp_usb_jtag.c:763 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1 Info : 278 13 core.c:1449 adapter_init(): clock speed 40000 kHz Debug: 279 13 openocd.c:141 handle_init_command(): Debug Adapter init complete Debug: 280 13 command.c:143 script_debug(): command - transport transport init Debug: 282 13 transport.c:239 handle_transport_init(): handle_transport_init Debug: 283 13 core.c:729 jtag_add_reset(): SRST line released Debug: 284 13 core.c:753 jtag_add_reset(): TRST line released Debug: 285 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 286 13 command.c:143 script_debug(): command - jtag jtag arp_init Debug: 287 13 core.c:1462 jtag_init_inner(): Init JTAG chain Debug: 288 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 289 13 core.c:1128 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS Debug: 290 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset Info : 291 14 core.c:1027 jtag_examine_chain_display(): JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0) Debug: 292 14 core.c:1258 jtag_validate_ircapture(): IR capture validation scan Debug: 293 14 core.c:1315 jtag_validate_ircapture(): esp32c3.cpu: IR capture 0x05 Debug: 294 14 command.c:143 script_debug(): command - dap dap init Debug: 296 14 arm_dap.c:106 dap_init_all(): Initializing all DAPs ... Debug: 297 14 openocd.c:158 handle_init_command(): Examining targets... Debug: 298 14 target.c:1636 target_call_event_callbacks(): target event 17 (examine-start) for core esp32c3 Debug: 299 14 riscv.c:983 riscv_examine(): riscv_examine() Debug: 300 14 riscv.c:407 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071 Debug: 301 14 riscv.c:993 riscv_examine(): dtmcontrol=0x1071 Debug: 302 14 riscv.c:995 riscv_examine(): version=0x1 Debug: 303 14 riscv-013.c:1773 init_target(): init Debug: 304 14 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071 Debug: 305 14 riscv-013.c:1484 examine(): dtmcontrol=0x1071 Debug: 306 14 riscv-013.c:1485 examine(): dmireset=0 Debug: 307 14 riscv-013.c:1486 examine(): idle=1 Debug: 308 14 riscv-013.c:1487 examine(): dmistat=0 Debug: 309 14 riscv-013.c:1488 examine(): abits=7 Debug: 310 14 riscv-013.c:1489 examine(): version=1 Debug: 311 14 riscv-013.c:264 get_dm(): [0] Allocating new DM Debug: 312 16 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0 Debug: 313 16 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71 Debug: 314 16 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0 Debug: 315 16 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071 Debug: 316 16 riscv-013.c:1532 examine(): dmstatus: 0x0003cca2 Debug: 317 16 riscv-013.c:1548 examine(): hartsellen=20 Debug: 318 17 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0 Debug: 319 17 riscv-013.c:453 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071 Info : 320 17 riscv-013.c:1579 examine(): datacount=2 progbufsize=16 Debug: 321 19 riscv-013.c:1617 examine(): Detected 1 harts. Debug: 322 20 riscv-013.c:3588 select_prepped_harts(): index=0, coreid=0, prepped=0 Debug: 323 20 riscv-013.c:3629 riscv013_halt_go(): halting hart 0 Debug: 324 21 riscv-013.c:776 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 325 21 riscv-013.c:799 execute_abstract_command(): command 0x321008 failed; abstractcs=0x10000202 Debug: 326 21 riscv-013.c:776 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 327 22 riscv-013.c:1426 register_read_direct(): {0} misa = 0x40101104 Debug: 328 22 riscv.c:3344 riscv_init_registers(): create register cache for 4162 registers Debug: 329 23 riscv-013.c:1669 examine(): hart 0: XLEN=32, misa=0x40101104 Debug: 330 23 riscv-013.c:4210 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0) Info : 331 24 riscv-013.c:1693 examine(): Examined RISC-V core; found 1 harts Info : 332 24 riscv-013.c:1697 examine(): hart 0: XLEN=32, misa=0x40101104 Debug: 333 24 target.c:1636 target_call_event_callbacks(): target event 18 (examine-end) for core esp32c3 Debug: 334 24 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 18 (examine-end) action:

Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default

arm semihosting enable
arm semihosting_resexit enable

Debug: 335 24 command.c:143 script_debug(): command - arm arm semihosting enable Debug: 336 25 riscv.c:1828 riscv_poll_hart(): triggered running Debug: 338 25 riscv_semihosting.c:181 riscv_semihosting_setup(): enable=1 Debug: 339 25 command.c:143 script_debug(): command - arm arm semihosting_resexit enable Debug: 341 25 command.c:143 script_debug(): command - flash flash init Debug: 343 25 tcl.c:1222 handle_flash_init_command(): Initializing flash devices... Debug: 344 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 345 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 346 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 347 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 348 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 349 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 350 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 351 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 352 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 353 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 354 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 355 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 356 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 357 25 command.c:355 register_command_handler(): registering 'flash'... Debug: 358 25 command.c:143 script_debug(): command - nand nand init Debug: 360 26 tcl.c:498 handle_nand_init_command(): Initializing NAND devices... Debug: 361 26 command.c:143 script_debug(): command - pld pld init Debug: 363 26 pld.c:206 handle_pld_init_command(): Initializing PLDs... Debug: 364 26 gdb_server.c:3584 gdb_target_start(): starting gdb server for esp32c3 on 3333 Info : 365 26 server.c:310 add_service(): Listening on port 3333 for gdb connections Info : 366 7423 server.c:100 add_connection(): accepting 'gdb' connection on tcp/3333 Debug: 367 7424 breakpoints.c:357 breakpoint_clear_target_internal(): Delete all breakpoints for target: esp32c3 Debug: 368 7424 breakpoints.c:551 watchpoint_clear_target(): Delete all watchpoints for target: esp32c3 Debug: 369 7424 FreeRTOS.c:1197 FreeRTOS_clean(): FreeRTOS_clean Debug: 370 7424 FreeRTOS.c:708 FreeRTOS_update_threads(): FreeRTOS_update_threads Warn : 371 7424 FreeRTOS.c:716 FreeRTOS_update_threads(): No symbols for FreeRTOS! Debug: 372 7424 target.c:1636 target_call_event_callbacks(): target event 19 (gdb-attach) for core esp32c3 Debug: 373 7424 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 19 (gdb-attach) action:

'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map

halt
# by default mask interrupts while stepping
riscv maskisr steponly

Debug: 374 7424 command.c:143 script_debug(): command - halt halt Debug: 376 7425 target.c:3135 handle_halt_command(): - Debug: 377 7425 riscv.c:1097 riscv_halt(): [0] halting all harts Debug: 378 7425 riscv.c:1030 halt_prep(): prep hart 0 Debug: 379 7426 riscv-013.c:3588 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 380 7426 riscv-013.c:3629 riscv013_halt_go(): halting hart 0 Debug: 381 7427 riscv.c:2909 riscv_invalidate_register_cache(): [0] Debug: 382 7428 target.c:1636 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 383 7428 target.c:1636 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 384 7428 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable Debug: 385 7428 command.c:143 script_debug(): command - command command mode Debug: 386 7428 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1 Debug: 388 7429 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 389 7429 command.c:143 script_debug(): command - mww mww 0x6001F048 0 Debug: 391 7430 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 392 7430 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1 Debug: 394 7431 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 395 7432 command.c:143 script_debug(): command - mww mww 0x60020048 0 Debug: 397 7433 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 398 7433 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1 Debug: 400 7434 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 401 7435 command.c:143 script_debug(): command - mww mww 0x60008090 0 Debug: 403 7436 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 404 7436 command.c:143 script_debug(): command - mww mww 0x600080b0 0x8F1D312A Debug: 406 7437 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 407 7437 command.c:143 script_debug(): command - mww mww 0x600080ac 0x84B00000 Debug: 409 7438 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 410 7439 command.c:143 script_debug(): command - riscv riscv maskisr steponly Debug: 412 7439 esp_flash.c:911 esp_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32c3' - 'halted' Debug: 413 7439 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 414 7439 algorithm.c:336 algorithm_load_func_image(): stub: base 0x0, start 0x403816d6, 2 sections Debug: 415 7439 algorithm.c:344 algorithm_load_func_image(): addr 0x00000000, sz 7640, flags 1 Debug: 416 7439 target.c:1835 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x40380000 Debug: 417 7439 target.c:1890 alloc_working_area_try_do(): allocated new working area of 7640 bytes at address 0x40380000 Debug: 418 7439 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:1910 start address: 0x40380000 Debug: 419 7440 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380000 Debug: 420 7441 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380080 Debug: 421 7442 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380100 Debug: 422 7443 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380180 Debug: 423 7444 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380200 Debug: 424 7446 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380280 Debug: 425 7447 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380300 Debug: 426 7448 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380380 Debug: 427 7449 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380400 Debug: 428 7450 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380480 Debug: 429 7452 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380500 Debug: 430 7453 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380580 Debug: 431 7454 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380600 Debug: 432 7455 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380680 Debug: 433 7456 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380700 Debug: 434 7457 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380780 Debug: 435 7459 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380800 Debug: 436 7460 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380880 Debug: 437 7461 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380900 Debug: 438 7462 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380980 Debug: 439 7463 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380a00 Debug: 440 7465 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380a80 Debug: 441 7466 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380b00 Debug: 442 7467 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380b80 Debug: 443 7468 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380c00 Debug: 444 7469 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380c80 Debug: 445 7470 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380d00 Debug: 446 7471 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380d80 Debug: 447 7473 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380e00 Debug: 448 7474 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380e80 Debug: 449 7475 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380f00 Debug: 450 7476 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40380f80 Debug: 451 7477 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381000 Debug: 452 7479 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381080 Debug: 453 7480 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381100 Debug: 454 7481 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381180 Debug: 455 7482 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381200 Debug: 456 7484 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381280 Debug: 457 7485 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381300 Debug: 458 7486 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381380 Debug: 459 7487 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381400 Debug: 460 7488 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381480 Debug: 461 7489 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381500 Debug: 462 7491 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381580 Debug: 463 7492 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381600 Debug: 464 7493 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381680 Debug: 465 7494 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381700 Debug: 466 7495 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381780 Debug: 467 7496 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381800 Debug: 468 7498 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381880 Debug: 469 7499 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381900 Debug: 470 7500 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381980 Debug: 471 7501 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381a00 Debug: 472 7502 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381a80 Debug: 473 7503 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381b00 Debug: 474 7505 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381b80 Debug: 475 7505 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381c00 Debug: 476 7506 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381c80 Debug: 477 7508 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381d00 Debug: 478 7509 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381d80 Debug: 479 7510 target.c:1751 print_wa_layout(): b* 0x40380000-0x40381dd7 (7640 bytes) Debug: 480 7510 target.c:1751 print_wa_layout(): 0x40381dd8-0x40383fff (8744 bytes) Debug: 481 7510 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380000 Debug: 482 7510 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 483 7512 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 484 7514 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 485 7516 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 486 7517 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380200 Debug: 487 7518 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 488 7520 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 489 7521 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 490 7523 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 491 7525 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380400 Debug: 492 7526 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 493 7527 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 494 7529 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 495 7531 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 496 7533 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380600 Debug: 497 7534 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 498 7536 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 499 7538 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 500 7539 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 501 7541 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380800 Debug: 502 7542 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 503 7543 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 504 7545 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 505 7547 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 506 7548 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380a00 Debug: 507 7549 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 508 7551 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 509 7553 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 510 7554 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 511 7556 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380c00 Debug: 512 7557 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 513 7559 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 514 7561 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 515 7563 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 516 7564 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40380e00 Debug: 517 7565 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 518 7566 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 519 7568 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 520 7570 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 521 7572 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381000 Debug: 522 7573 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 523 7574 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 524 7576 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 525 7578 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 526 7580 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381200 Debug: 527 7580 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 528 7582 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 529 7584 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 530 7586 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 531 7588 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381400 Debug: 532 7588 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 533 7590 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 534 7592 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 535 7594 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 536 7596 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381600 Debug: 537 7596 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 538 7598 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 539 7600 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 540 7602 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 541 7604 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381800 Debug: 542 7604 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 543 7606 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 544 7608 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 545 7610 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 546 7611 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381a00 Debug: 547 7612 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 548 7614 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 549 7615 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 550 7617 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 551 7619 target.c:2237 target_write_buffer(): writing buffer of 472 byte at 0x40381c00 Debug: 552 7619 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 553 7621 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 554 7623 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 555 7624 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 556 7626 algorithm.c:344 algorithm_load_func_image(): addr 0x00000000, sz 637, flags 0 Debug: 557 7626 target.c:1835 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x3fc84000 Debug: 558 7626 target.c:1890 alloc_working_area_try_do(): allocated new working area of 920 bytes at address 0x3fc84000 Debug: 559 7626 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:230 start address: 0x3fc84000 Debug: 560 7626 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84000 Debug: 561 7627 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84080 Debug: 562 7629 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84100 Debug: 563 7630 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84180 Debug: 564 7631 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84200 Debug: 565 7632 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84280 Debug: 566 7633 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84300 Debug: 567 7634 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84380 Debug: 568 7634 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 569 7634 target.c:1751 print_wa_layout(): 0x3fc84398-0x3fca3fff (130152 bytes) Debug: 570 7634 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000 Debug: 571 7635 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 572 7637 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 573 7638 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 574 7640 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 575 7642 target.c:2237 target_write_buffer(): writing buffer of 125 byte at 0x3fc84200 Debug: 576 7642 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 577 7644 riscv-013.c:3226 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc8427c Debug: 578 7644 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 579 7645 riscv-013.c:1426 register_read_direct(): {0} s0 = 0x3fc9a2b0 Debug: 580 7645 riscv-013.c:776 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 581 7646 riscv-013.c:1426 register_read_direct(): {0} s1 = 0x1 Debug: 582 7646 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x00940023) Debug: 583 7646 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x00140413) Debug: 584 7646 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 585 7647 riscv-013.c:3283 write_memory_progbuf(): writing until final address 0x000000003fc8427d Debug: 586 7647 riscv-013.c:3285 write_memory_progbuf(): transferring burst starting at address 0x000000003fc8427c Debug: 587 7647 riscv-013.c:1238 register_write_direct(): {0} s0 <- 0x3fc8427c Debug: 588 7647 riscv-013.c:776 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 589 7648 riscv-013.c:776 execute_abstract_command(): command=0x271009; access register, size=32, postexec=1, transfer=1, write=1, regno=0x1009 Debug: 590 7648 batch.c:50 riscv_batch_run(): Ignoring empty batch. Debug: 591 7649 riscv-013.c:3363 write_memory_progbuf(): successful (partial?) memory write Debug: 592 7649 riscv-013.c:1238 register_write_direct(): {0} s1 <- 0x1 Debug: 593 7649 riscv-013.c:776 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 594 7650 riscv-013.c:1238 register_write_direct(): {0} s0 <- 0x3fc9a2b0 Debug: 595 7650 riscv-013.c:776 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 596 7651 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 597 7651 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 598 7651 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 599 7651 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 600 7651 riscv-013.c:776 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 601 7652 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 602 7652 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100f @0 Debug: 603 7652 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 604 7652 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0xf @1 Debug: 605 7652 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 606 7652 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 607 7652 riscv-013.c:776 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 608 7652 target.c:1890 alloc_working_area_try_do(): allocated new working area of 1300 bytes at address 0x3fc84398 Debug: 609 7652 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:325 start address: 0x3fc84398 Debug: 610 7653 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84398 Debug: 611 7654 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84418 Debug: 612 7655 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84498 Debug: 613 7656 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84518 Debug: 614 7657 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84598 Debug: 615 7658 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84618 Debug: 616 7660 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84698 Debug: 617 7661 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84718 Debug: 618 7662 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84798 Debug: 619 7663 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84818 Debug: 620 7664 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84898 Debug: 621 7664 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 622 7664 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 623 7664 target.c:1751 print_wa_layout(): 0x3fc848ac-0x3fca3fff (128852 bytes) Debug: 624 7664 target.c:1890 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381dd8 Debug: 625 7664 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:1 start address: 0x40381dd8 Debug: 626 7665 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381dd8 Debug: 627 7665 target.c:1751 print_wa_layout(): b 0x40380000-0x40381dd7 (7640 bytes) Debug: 628 7665 target.c:1751 print_wa_layout(): b 0x40381dd8-0x40381ddb (4 bytes) Debug: 629 7665 target.c:1751 print_wa_layout(): 0x40381ddc-0x40383fff (8740 bytes) Debug: 630 7665 target.c:2237 target_write_buffer(): writing buffer of 4 byte at 0x40381dd8 Debug: 631 7666 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381dd8 Debug: 632 7666 algorithm.c:455 algorithm_load_func_image(): Stub loaded in 227.29 ms Debug: 633 7666 riscv_algorithm.c:53 riscv_algo_regs_init_start(): Check stack addr 0x3fc848ac Debug: 634 7666 riscv_algorithm.c:56 riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc848a0 Debug: 635 7666 riscv_algorithm.c:95 riscv_algo_init(): Set arg[0] = 5 (a0) Debug: 636 7666 riscv_algorithm.c:105 riscv_algo_init(): Set arg[1] = -1 (a1) Debug: 637 7666 riscv_algorithm.c:105 riscv_algo_init(): Set arg[2] = 0 (a2) Debug: 638 7666 target.c:1890 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x3fc848ac Debug: 639 7666 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:7 start address: 0x3fc848ac Debug: 640 7667 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc848ac Debug: 641 7667 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 642 7667 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 643 7667 target.c:1751 print_wa_layout(): b 0x3fc848ac-0x3fc848c7 (28 bytes) Debug: 644 7667 target.c:1751 print_wa_layout(): 0x3fc848c8-0x3fca3fff (128824 bytes) Debug: 645 7667 algorithm.c:223 algorithm_run(): Algorithm start @ 0x40381dd8, stack 1300 bytes @ 0x3fc848ac Debug: 646 7667 riscv.c:1484 riscv_start_algorithm(): save ra Debug: 647 7667 riscv-013.c:3491 riscv013_get_register(): [0] reading register ra on hart 0 Debug: 648 7667 riscv-013.c:776 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001 Debug: 649 7668 riscv-013.c:1426 register_read_direct(): {0} ra = 0x42067d46 Debug: 650 7668 riscv.c:3005 riscv_get_register_on_hart(): {0} ra: 42067d46 Debug: 651 7668 riscv.c:3281 register_get(): [0]{0} read 0x42067d46 from ra (valid=1) Debug: 652 7668 riscv.c:1484 riscv_start_algorithm(): save sp Debug: 653 7668 riscv-013.c:3491 riscv013_get_register(): [0] reading register sp on hart 0 Debug: 654 7668 riscv-013.c:776 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002 Debug: 655 7669 riscv-013.c:1426 register_read_direct(): {0} sp = 0x3fca1010 Debug: 656 7669 riscv.c:3005 riscv_get_register_on_hart(): {0} sp: 3fca1010 Debug: 657 7669 riscv.c:3281 register_get(): [0]{0} read 0x3fca1010 from sp (valid=1) Debug: 658 7669 riscv.c:1484 riscv_start_algorithm(): save gp Debug: 659 7669 riscv-013.c:3491 riscv013_get_register(): [0] reading register gp on hart 0 Debug: 660 7669 riscv-013.c:776 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003 Debug: 661 7670 riscv-013.c:1426 register_read_direct(): {0} gp = 0x3fc8f200 Debug: 662 7670 riscv.c:3005 riscv_get_register_on_hart(): {0} gp: 3fc8f200 Debug: 663 7670 riscv.c:3281 register_get(): [0]{0} read 0x3fc8f200 from gp (valid=1) Debug: 664 7670 riscv.c:1484 riscv_start_algorithm(): save tp Debug: 665 7670 riscv-013.c:3491 riscv013_get_register(): [0] reading register tp on hart 0 Debug: 666 7670 riscv-013.c:776 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004 Debug: 667 7670 riscv-013.c:1426 register_read_direct(): {0} tp = 0x3fc7c274 Debug: 668 7670 riscv.c:3005 riscv_get_register_on_hart(): {0} tp: 3fc7c274 Debug: 669 7670 riscv.c:3281 register_get(): [0]{0} read 0x3fc7c274 from tp (valid=1) Debug: 670 7670 riscv.c:1484 riscv_start_algorithm(): save t0 Debug: 671 7670 riscv-013.c:3491 riscv013_get_register(): [0] reading register t0 on hart 0 Debug: 672 7670 riscv-013.c:776 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005 Debug: 673 7671 riscv-013.c:1426 register_read_direct(): {0} t0 = 0x0 Debug: 674 7671 riscv.c:3005 riscv_get_register_on_hart(): {0} t0: 0 Debug: 675 7671 riscv.c:3281 register_get(): [0]{0} read 0x0 from t0 (valid=1) Debug: 676 7671 riscv.c:1484 riscv_start_algorithm(): save t1 Debug: 677 7671 riscv-013.c:3491 riscv013_get_register(): [0] reading register t1 on hart 0 Debug: 678 7671 riscv-013.c:776 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006 Debug: 679 7672 riscv-013.c:1426 register_read_direct(): {0} t1 = 0x4038d25c Debug: 680 7672 riscv.c:3005 riscv_get_register_on_hart(): {0} t1: 4038d25c Debug: 681 7672 riscv.c:3281 register_get(): [0]{0} read 0x4038d25c from t1 (valid=1) Debug: 682 7672 riscv.c:1484 riscv_start_algorithm(): save t2 Debug: 683 7672 riscv-013.c:3491 riscv013_get_register(): [0] reading register t2 on hart 0 Debug: 684 7672 riscv-013.c:776 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007 Debug: 685 7673 riscv-013.c:1426 register_read_direct(): {0} t2 = 0x0 Debug: 686 7673 riscv.c:3005 riscv_get_register_on_hart(): {0} t2: 0 Debug: 687 7673 riscv.c:3281 register_get(): [0]{0} read 0x0 from t2 (valid=1) Debug: 688 7673 riscv.c:1484 riscv_start_algorithm(): save fp Debug: 689 7673 riscv-013.c:3491 riscv013_get_register(): [0] reading register s0 on hart 0 Debug: 690 7673 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 691 7673 riscv-013.c:1426 register_read_direct(): {0} s0 = 0x3fc9a2b0 Debug: 692 7673 riscv.c:3005 riscv_get_register_on_hart(): {0} s0: 3fc9a2b0 Debug: 693 7673 riscv.c:3281 register_get(): [0]{0} read 0x3fc9a2b0 from fp (valid=1) Debug: 694 7673 riscv.c:1484 riscv_start_algorithm(): save s1 Debug: 695 7673 riscv-013.c:3491 riscv013_get_register(): [0] reading register s1 on hart 0 Debug: 696 7673 riscv-013.c:776 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 697 7674 riscv-013.c:1426 register_read_direct(): {0} s1 = 0x1 Debug: 698 7674 riscv.c:3005 riscv_get_register_on_hart(): {0} s1: 1 Debug: 699 7674 riscv.c:3281 register_get(): [0]{0} read 0x1 from s1 (valid=1) Debug: 700 7674 riscv.c:1484 riscv_start_algorithm(): save a0 Debug: 701 7674 riscv-013.c:3491 riscv013_get_register(): [0] reading register a0 on hart 0 Debug: 702 7674 riscv-013.c:776 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 703 7675 riscv-013.c:1426 register_read_direct(): {0} a0 = 0x1 Debug: 704 7675 riscv.c:3005 riscv_get_register_on_hart(): {0} a0: 1 Debug: 705 7675 riscv.c:3281 register_get(): [0]{0} read 0x1 from a0 (valid=1) Debug: 706 7675 riscv.c:1484 riscv_start_algorithm(): save a1 Debug: 707 7675 riscv-013.c:3491 riscv013_get_register(): [0] reading register a1 on hart 0 Debug: 708 7675 riscv-013.c:776 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b Debug: 709 7676 riscv-013.c:1426 register_read_direct(): {0} a1 = 0x3fca101f Debug: 710 7676 riscv.c:3005 riscv_get_register_on_hart(): {0} a1: 3fca101f Debug: 711 7676 riscv.c:3281 register_get(): [0]{0} read 0x3fca101f from a1 (valid=1) Debug: 712 7676 riscv.c:1484 riscv_start_algorithm(): save a2 Debug: 713 7676 riscv-013.c:3491 riscv013_get_register(): [0] reading register a2 on hart 0 Debug: 714 7676 riscv-013.c:776 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c Debug: 715 7676 riscv-013.c:1426 register_read_direct(): {0} a2 = 0x10 Debug: 716 7676 riscv.c:3005 riscv_get_register_on_hart(): {0} a2: 10 Debug: 717 7676 riscv.c:3281 register_get(): [0]{0} read 0x10 from a2 (valid=1) Debug: 718 7676 riscv.c:1484 riscv_start_algorithm(): save a3 Debug: 719 7676 riscv-013.c:3491 riscv013_get_register(): [0] reading register a3 on hart 0 Debug: 720 7676 riscv-013.c:776 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d Debug: 721 7677 riscv-013.c:1426 register_read_direct(): {0} a3 = 0x4 Debug: 722 7677 riscv.c:3005 riscv_get_register_on_hart(): {0} a3: 4 Debug: 723 7677 riscv.c:3281 register_get(): [0]{0} read 0x4 from a3 (valid=1) Debug: 724 7677 riscv.c:1484 riscv_start_algorithm(): save a4 Debug: 725 7677 riscv-013.c:3491 riscv013_get_register(): [0] reading register a4 on hart 0 Debug: 726 7677 riscv-013.c:776 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e Debug: 727 7678 riscv-013.c:1426 register_read_direct(): {0} a4 = 0x1 Debug: 728 7678 riscv.c:3005 riscv_get_register_on_hart(): {0} a4: 1 Debug: 729 7678 riscv.c:3281 register_get(): [0]{0} read 0x1 from a4 (valid=1) Debug: 730 7678 riscv.c:1484 riscv_start_algorithm(): save a5 Debug: 731 7678 riscv-013.c:3491 riscv013_get_register(): [0] reading register a5 on hart 0 Debug: 732 7678 riscv-013.c:776 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f Debug: 733 7679 riscv-013.c:1426 register_read_direct(): {0} a5 = 0x3fc9d000 Debug: 734 7679 riscv.c:3005 riscv_get_register_on_hart(): {0} a5: 3fc9d000 Debug: 735 7679 riscv.c:3281 register_get(): [0]{0} read 0x3fc9d000 from a5 (valid=1) Debug: 736 7679 riscv.c:1484 riscv_start_algorithm(): save a6 Debug: 737 7679 riscv-013.c:3491 riscv013_get_register(): [0] reading register a6 on hart 0 Debug: 738 7679 riscv-013.c:776 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010 Debug: 739 7679 riscv-013.c:1426 register_read_direct(): {0} a6 = 0x0 Debug: 740 7679 riscv.c:3005 riscv_get_register_on_hart(): {0} a6: 0 Debug: 741 7679 riscv.c:3281 register_get(): [0]{0} read 0x0 from a6 (valid=1) Debug: 742 7679 riscv.c:1484 riscv_start_algorithm(): save a7 Debug: 743 7679 riscv-013.c:3491 riscv013_get_register(): [0] reading register a7 on hart 0 Debug: 744 7679 riscv-013.c:776 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011 Debug: 745 7680 riscv-013.c:1426 register_read_direct(): {0} a7 = 0x0 Debug: 746 7680 riscv.c:3005 riscv_get_register_on_hart(): {0} a7: 0 Debug: 747 7680 riscv.c:3281 register_get(): [0]{0} read 0x0 from a7 (valid=1) Debug: 748 7680 riscv.c:1484 riscv_start_algorithm(): save s2 Debug: 749 7680 riscv-013.c:3491 riscv013_get_register(): [0] reading register s2 on hart 0 Debug: 750 7680 riscv-013.c:776 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012 Debug: 751 7681 riscv-013.c:1426 register_read_direct(): {0} s2 = 0x3fc9a2d0 Debug: 752 7681 riscv.c:3005 riscv_get_register_on_hart(): {0} s2: 3fc9a2d0 Debug: 753 7681 riscv.c:3281 register_get(): [0]{0} read 0x3fc9a2d0 from s2 (valid=1) Debug: 754 7681 riscv.c:1484 riscv_start_algorithm(): save s3 Debug: 755 7681 riscv-013.c:3491 riscv013_get_register(): [0] reading register s3 on hart 0 Debug: 756 7681 riscv-013.c:776 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013 Debug: 757 7682 riscv-013.c:1426 register_read_direct(): {0} s3 = 0x7fffffff Debug: 758 7682 riscv.c:3005 riscv_get_register_on_hart(): {0} s3: 7fffffff Debug: 759 7682 riscv.c:3281 register_get(): [0]{0} read 0x7fffffff from s3 (valid=1) Debug: 760 7682 riscv.c:1484 riscv_start_algorithm(): save s4 Debug: 761 7682 riscv-013.c:3491 riscv013_get_register(): [0] reading register s4 on hart 0 Debug: 762 7682 riscv-013.c:776 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014 Debug: 763 7683 riscv-013.c:1426 register_read_direct(): {0} s4 = 0x3fc92a8c Debug: 764 7683 riscv.c:3005 riscv_get_register_on_hart(): {0} s4: 3fc92a8c Debug: 765 7683 riscv.c:3281 register_get(): [0]{0} read 0x3fc92a8c from s4 (valid=1) Debug: 766 7683 riscv.c:1484 riscv_start_algorithm(): save s5 Debug: 767 7683 riscv-013.c:3491 riscv013_get_register(): [0] reading register s5 on hart 0 Debug: 768 7683 riscv-013.c:776 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015 Debug: 769 7683 riscv-013.c:1426 register_read_direct(): {0} s5 = 0x3fc9d000 Debug: 770 7683 riscv.c:3005 riscv_get_register_on_hart(): {0} s5: 3fc9d000 Debug: 771 7683 riscv.c:3281 register_get(): [0]{0} read 0x3fc9d000 from s5 (valid=1) Debug: 772 7683 riscv.c:1484 riscv_start_algorithm(): save s6 Debug: 773 7683 riscv-013.c:3491 riscv013_get_register(): [0] reading register s6 on hart 0 Debug: 774 7683 riscv-013.c:776 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016 Debug: 775 7684 riscv-013.c:1426 register_read_direct(): {0} s6 = 0x0 Debug: 776 7684 riscv.c:3005 riscv_get_register_on_hart(): {0} s6: 0 Debug: 777 7684 riscv.c:3281 register_get(): [0]{0} read 0x0 from s6 (valid=1) Debug: 778 7684 riscv.c:1484 riscv_start_algorithm(): save s7 Debug: 779 7684 riscv-013.c:3491 riscv013_get_register(): [0] reading register s7 on hart 0 Debug: 780 7684 riscv-013.c:776 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017 Debug: 781 7685 riscv-013.c:1426 register_read_direct(): {0} s7 = 0x0 Debug: 782 7685 riscv.c:3005 riscv_get_register_on_hart(): {0} s7: 0 Debug: 783 7685 riscv.c:3281 register_get(): [0]{0} read 0x0 from s7 (valid=1) Debug: 784 7685 riscv.c:1484 riscv_start_algorithm(): save s8 Debug: 785 7685 riscv-013.c:3491 riscv013_get_register(): [0] reading register s8 on hart 0 Debug: 786 7685 riscv-013.c:776 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018 Debug: 787 7686 riscv-013.c:1426 register_read_direct(): {0} s8 = 0x0 Debug: 788 7686 riscv.c:3005 riscv_get_register_on_hart(): {0} s8: 0 Debug: 789 7686 riscv.c:3281 register_get(): [0]{0} read 0x0 from s8 (valid=1) Debug: 790 7686 riscv.c:1484 riscv_start_algorithm(): save s9 Debug: 791 7686 riscv-013.c:3491 riscv013_get_register(): [0] reading register s9 on hart 0 Debug: 792 7686 riscv-013.c:776 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019 Debug: 793 7686 riscv-013.c:1426 register_read_direct(): {0} s9 = 0x0 Debug: 794 7686 riscv.c:3005 riscv_get_register_on_hart(): {0} s9: 0 Debug: 795 7686 riscv.c:3281 register_get(): [0]{0} read 0x0 from s9 (valid=1) Debug: 796 7686 riscv.c:1484 riscv_start_algorithm(): save s10 Debug: 797 7686 riscv-013.c:3491 riscv013_get_register(): [0] reading register s10 on hart 0 Debug: 798 7686 riscv-013.c:776 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a Debug: 799 7687 riscv-013.c:1426 register_read_direct(): {0} s10 = 0x0 Debug: 800 7687 riscv.c:3005 riscv_get_register_on_hart(): {0} s10: 0 Debug: 801 7687 riscv.c:3281 register_get(): [0]{0} read 0x0 from s10 (valid=1) Debug: 802 7687 riscv.c:1484 riscv_start_algorithm(): save s11 Debug: 803 7687 riscv-013.c:3491 riscv013_get_register(): [0] reading register s11 on hart 0 Debug: 804 7687 riscv-013.c:776 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b Debug: 805 7688 riscv-013.c:1426 register_read_direct(): {0} s11 = 0x0 Debug: 806 7688 riscv.c:3005 riscv_get_register_on_hart(): {0} s11: 0 Debug: 807 7688 riscv.c:3281 register_get(): [0]{0} read 0x0 from s11 (valid=1) Debug: 808 7688 riscv.c:1484 riscv_start_algorithm(): save t3 Debug: 809 7688 riscv-013.c:3491 riscv013_get_register(): [0] reading register t3 on hart 0 Debug: 810 7688 riscv-013.c:776 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c Debug: 811 7688 riscv-013.c:1426 register_read_direct(): {0} t3 = 0x0 Debug: 812 7688 riscv.c:3005 riscv_get_register_on_hart(): {0} t3: 0 Debug: 813 7688 riscv.c:3281 register_get(): [0]{0} read 0x0 from t3 (valid=1) Debug: 814 7688 riscv.c:1484 riscv_start_algorithm(): save t4 Debug: 815 7688 riscv-013.c:3491 riscv013_get_register(): [0] reading register t4 on hart 0 Debug: 816 7688 riscv-013.c:776 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d Debug: 817 7689 riscv-013.c:1426 register_read_direct(): {0} t4 = 0x0 Debug: 818 7689 riscv.c:3005 riscv_get_register_on_hart(): {0} t4: 0 Debug: 819 7689 riscv.c:3281 register_get(): [0]{0} read 0x0 from t4 (valid=1) Debug: 820 7689 riscv.c:1484 riscv_start_algorithm(): save t5 Debug: 821 7689 riscv-013.c:3491 riscv013_get_register(): [0] reading register t5 on hart 0 Debug: 822 7689 riscv-013.c:776 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e Debug: 823 7690 riscv-013.c:1426 register_read_direct(): {0} t5 = 0x0 Debug: 824 7690 riscv.c:3005 riscv_get_register_on_hart(): {0} t5: 0 Debug: 825 7690 riscv.c:3281 register_get(): [0]{0} read 0x0 from t5 (valid=1) Debug: 826 7690 riscv.c:1484 riscv_start_algorithm(): save t6 Debug: 827 7690 riscv-013.c:3491 riscv013_get_register(): [0] reading register t6 on hart 0 Debug: 828 7690 riscv-013.c:776 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f Debug: 829 7691 riscv-013.c:1426 register_read_direct(): {0} t6 = 0x0 Debug: 830 7691 riscv.c:3005 riscv_get_register_on_hart(): {0} t6: 0 Debug: 831 7691 riscv.c:3281 register_get(): [0]{0} read 0x0 from t6 (valid=1) Debug: 832 7691 riscv.c:1484 riscv_start_algorithm(): save pc Debug: 833 7691 riscv-013.c:3491 riscv013_get_register(): [0] reading register pc on hart 0 Debug: 834 7691 riscv-013.c:776 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 835 7691 riscv-013.c:1426 register_read_direct(): {0} dpc = 0x4038a4ee Debug: 836 7691 riscv-013.c:3499 riscv013_get_register(): [0] read PC from DPC: 0x4038a4ee Debug: 837 7691 riscv.c:3005 riscv_get_register_on_hart(): {0} pc: 4038a4ee Debug: 838 7691 riscv.c:3281 register_get(): [0]{0} read 0x4038a4ee from pc (valid=1) Debug: 839 7691 riscv.c:1484 riscv_start_algorithm(): save mstatus Debug: 840 7691 riscv-013.c:3491 riscv013_get_register(): [0] reading register mstatus on hart 0 Debug: 841 7691 riscv-013.c:776 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 842 7692 riscv-013.c:1426 register_read_direct(): {0} mstatus = 0x89 Debug: 843 7692 riscv.c:3005 riscv_get_register_on_hart(): {0} mstatus: 89 Debug: 844 7692 riscv.c:3281 register_get(): [0]{0} read 0x89 from mstatus (valid=0) Debug: 845 7692 riscv.c:1484 riscv_start_algorithm(): save misa Debug: 846 7692 riscv-013.c:3491 riscv013_get_register(): [0] reading register misa on hart 0 Debug: 847 7692 riscv-013.c:776 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 848 7693 riscv-013.c:1426 register_read_direct(): {0} misa = 0x40101104 Debug: 849 7693 riscv.c:3005 riscv_get_register_on_hart(): {0} misa: 40101104 Debug: 850 7693 riscv.c:3281 register_get(): [0]{0} read 0x40101104 from misa (valid=0) Debug: 851 7693 riscv.c:1484 riscv_start_algorithm(): save mtvec Debug: 852 7693 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr773 on hart 0 Debug: 853 7693 riscv-013.c:776 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 854 7693 riscv-013.c:1426 register_read_direct(): {0} csr773 = 0x40380001 Debug: 855 7693 riscv.c:3005 riscv_get_register_on_hart(): {0} csr773: 40380001 Debug: 856 7693 riscv.c:3281 register_get(): [0]{0} read 0x40380001 from mtvec (valid=0) Debug: 857 7693 riscv.c:1484 riscv_start_algorithm(): save mscratch Debug: 858 7693 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr832 on hart 0 Debug: 859 7693 riscv-013.c:776 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 860 7694 riscv-013.c:1426 register_read_direct(): {0} csr832 = 0x0 Debug: 861 7694 riscv.c:3005 riscv_get_register_on_hart(): {0} csr832: 0 Debug: 862 7694 riscv.c:3281 register_get(): [0]{0} read 0x0 from mscratch (valid=0) Debug: 863 7694 riscv.c:1484 riscv_start_algorithm(): save mepc Debug: 864 7694 riscv-013.c:3491 riscv013_get_register(): [0] reading register mepc on hart 0 Debug: 865 7694 riscv-013.c:776 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 866 7695 riscv-013.c:1426 register_read_direct(): {0} mepc = 0x40388b90 Debug: 867 7695 riscv.c:3005 riscv_get_register_on_hart(): {0} mepc: 40388b90 Debug: 868 7695 riscv.c:3281 register_get(): [0]{0} read 0x40388b90 from mepc (valid=0) Debug: 869 7695 riscv.c:1484 riscv_start_algorithm(): save mcause Debug: 870 7695 riscv-013.c:3491 riscv013_get_register(): [0] reading register mcause on hart 0 Debug: 871 7695 riscv-013.c:776 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 872 7696 riscv-013.c:1426 register_read_direct(): {0} mcause = 0x80000003 Debug: 873 7696 riscv.c:3005 riscv_get_register_on_hart(): {0} mcause: 80000003 Debug: 874 7696 riscv.c:3281 register_get(): [0]{0} read 0x80000003 from mcause (valid=0) Debug: 875 7696 riscv.c:1484 riscv_start_algorithm(): save mtval Debug: 876 7696 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr835 on hart 0 Debug: 877 7696 riscv-013.c:776 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 878 7696 riscv-013.c:1426 register_read_direct(): {0} csr835 = 0xe219 Debug: 879 7696 riscv.c:3005 riscv_get_register_on_hart(): {0} csr835: e219 Debug: 880 7696 riscv.c:3281 register_get(): [0]{0} read 0xe219 from mtval (valid=0) Debug: 881 7696 riscv.c:1484 riscv_start_algorithm(): save pmpcfg0 Debug: 882 7696 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr928 on hart 0 Debug: 883 7696 riscv-013.c:776 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 884 7697 riscv-013.c:1426 register_read_direct(): {0} csr928 = 0x89888f88 Debug: 885 7697 riscv.c:3005 riscv_get_register_on_hart(): {0} csr928: 89888f88 Debug: 886 7697 riscv.c:3281 register_get(): [0]{0} read 0x89888f88 from pmpcfg0 (valid=0) Debug: 887 7697 riscv.c:1484 riscv_start_algorithm(): save pmpcfg1 Debug: 888 7697 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr929 on hart 0 Debug: 889 7697 riscv-013.c:776 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 890 7698 riscv-013.c:1426 register_read_direct(): {0} csr929 = 0x888d898b Debug: 891 7698 riscv.c:3005 riscv_get_register_on_hart(): {0} csr929: 888d898b Debug: 892 7698 riscv.c:3281 register_get(): [0]{0} read 0x888d898b from pmpcfg1 (valid=0) Debug: 893 7698 riscv.c:1484 riscv_start_algorithm(): save pmpcfg2 Debug: 894 7698 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr930 on hart 0 Debug: 895 7698 riscv-013.c:776 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 896 7698 riscv-013.c:1426 register_read_direct(): {0} csr930 = 0x8f888d8f Debug: 897 7698 riscv.c:3005 riscv_get_register_on_hart(): {0} csr930: 8f888d8f Debug: 898 7698 riscv.c:3281 register_get(): [0]{0} read 0x8f888d8f from pmpcfg2 (valid=0) Debug: 899 7698 riscv.c:1484 riscv_start_algorithm(): save pmpcfg3 Debug: 900 7698 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr931 on hart 0 Debug: 901 7698 riscv-013.c:776 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 Debug: 902 7699 riscv-013.c:1426 register_read_direct(): {0} csr931 = 0x90888b88 Debug: 903 7699 riscv.c:3005 riscv_get_register_on_hart(): {0} csr931: 90888b88 Debug: 904 7699 riscv.c:3281 register_get(): [0]{0} read 0x90888b88 from pmpcfg3 (valid=0) Debug: 905 7699 riscv.c:1484 riscv_start_algorithm(): save pmpaddr0 Debug: 906 7699 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr944 on hart 0 Debug: 907 7699 riscv-013.c:776 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 908 7700 riscv-013.c:1426 register_read_direct(): {0} csr944 = 0x8000000 Debug: 909 7700 riscv.c:3005 riscv_get_register_on_hart(): {0} csr944: 8000000 Debug: 910 7700 riscv.c:3281 register_get(): [0]{0} read 0x8000000 from pmpaddr0 (valid=0) Debug: 911 7700 riscv.c:1484 riscv_start_algorithm(): save pmpaddr1 Debug: 912 7700 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr945 on hart 0 Debug: 913 7700 riscv-013.c:776 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 914 7701 riscv-013.c:1426 register_read_direct(): {0} csr945 = 0xa000000 Debug: 915 7701 riscv.c:3005 riscv_get_register_on_hart(): {0} csr945: a000000 Debug: 916 7701 riscv.c:3281 register_get(): [0]{0} read 0xa000000 from pmpaddr1 (valid=0) Debug: 917 7701 riscv.c:1484 riscv_start_algorithm(): save pmpaddr2 Debug: 918 7701 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr946 on hart 0 Debug: 919 7701 riscv-013.c:776 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 920 7702 riscv-013.c:1426 register_read_direct(): {0} csr946 = 0xf000000 Debug: 921 7702 riscv.c:3005 riscv_get_register_on_hart(): {0} csr946: f000000 Debug: 922 7702 riscv.c:3281 register_get(): [0]{0} read 0xf000000 from pmpaddr2 (valid=0) Debug: 923 7702 riscv.c:1484 riscv_start_algorithm(): save pmpaddr3 Debug: 924 7702 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr947 on hart 0 Debug: 925 7702 riscv-013.c:776 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 926 7702 riscv-013.c:1426 register_read_direct(): {0} csr947 = 0xff20000 Debug: 927 7702 riscv.c:3005 riscv_get_register_on_hart(): {0} csr947: ff20000 Debug: 928 7702 riscv.c:3281 register_get(): [0]{0} read 0xff20000 from pmpaddr3 (valid=0) Debug: 929 7702 riscv.c:1484 riscv_start_algorithm(): save pmpaddr4 Debug: 930 7702 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr948 on hart 0 Debug: 931 7702 riscv-013.c:776 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 932 7703 riscv-013.c:1426 register_read_direct(): {0} csr948 = 0xff38000 Debug: 933 7703 riscv.c:3005 riscv_get_register_on_hart(): {0} csr948: ff38000 Debug: 934 7703 riscv.c:3281 register_get(): [0]{0} read 0xff38000 from pmpaddr4 (valid=0) Debug: 935 7703 riscv.c:1484 riscv_start_algorithm(): save pmpaddr5 Debug: 936 7703 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr949 on hart 0 Debug: 937 7703 riscv-013.c:776 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 938 7703 riscv-013.c:1426 register_read_direct(): {0} csr949 = 0xffc8000 Debug: 939 7703 riscv.c:3005 riscv_get_register_on_hart(): {0} csr949: ffc8000 Debug: 940 7703 riscv.c:3281 register_get(): [0]{0} read 0xffc8000 from pmpaddr5 (valid=0) Debug: 941 7704 riscv.c:1484 riscv_start_algorithm(): save pmpaddr6 Debug: 942 7704 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr950 on hart 0 Debug: 943 7704 riscv-013.c:776 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 944 7704 riscv-013.c:1426 register_read_direct(): {0} csr950 = 0x10018000 Debug: 945 7704 riscv.c:3005 riscv_get_register_on_hart(): {0} csr950: 10018000 Debug: 946 7704 riscv.c:3281 register_get(): [0]{0} read 0x10018000 from pmpaddr6 (valid=0) Debug: 947 7704 riscv.c:1484 riscv_start_algorithm(): save pmpaddr7 Debug: 948 7704 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr951 on hart 0 Debug: 949 7704 riscv-013.c:776 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 950 7705 riscv-013.c:1426 register_read_direct(): {0} csr951 = 0x100df000 Debug: 951 7705 riscv.c:3005 riscv_get_register_on_hart(): {0} csr951: 100df000 Debug: 952 7705 riscv.c:3281 register_get(): [0]{0} read 0x100df000 from pmpaddr7 (valid=0) Debug: 953 7705 riscv.c:1484 riscv_start_algorithm(): save pmpaddr8 Debug: 954 7705 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr952 on hart 0 Debug: 955 7705 riscv-013.c:776 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 956 7706 riscv-013.c:1426 register_read_direct(): {0} csr952 = 0x100f8000 Debug: 957 7706 riscv.c:3005 riscv_get_register_on_hart(): {0} csr952: 100f8000 Debug: 958 7706 riscv.c:3281 register_get(): [0]{0} read 0x100f8000 from pmpaddr8 (valid=0) Debug: 959 7706 riscv.c:1484 riscv_start_algorithm(): save pmpaddr9 Debug: 960 7706 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr953 on hart 0 Debug: 961 7706 riscv-013.c:776 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 962 7706 riscv-013.c:1426 register_read_direct(): {0} csr953 = 0x10a00000 Debug: 963 7706 riscv.c:3005 riscv_get_register_on_hart(): {0} csr953: 10a00000 Debug: 964 7706 riscv.c:3281 register_get(): [0]{0} read 0x10a00000 from pmpaddr9 (valid=0) Debug: 965 7706 riscv.c:1484 riscv_start_algorithm(): save pmpaddr10 Debug: 966 7706 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr954 on hart 0 Debug: 967 7706 riscv-013.c:776 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 968 7707 riscv-013.c:1426 register_read_direct(): {0} csr954 = 0x14000000 Debug: 969 7707 riscv.c:3005 riscv_get_register_on_hart(): {0} csr954: 14000000 Debug: 970 7707 riscv.c:3281 register_get(): [0]{0} read 0x14000000 from pmpaddr10 (valid=0) Debug: 971 7707 riscv.c:1484 riscv_start_algorithm(): save pmpaddr11 Debug: 972 7707 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr955 on hart 0 Debug: 973 7707 riscv-013.c:776 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 974 7708 riscv-013.c:1426 register_read_direct(): {0} csr955 = 0x14000800 Debug: 975 7708 riscv.c:3005 riscv_get_register_on_hart(): {0} csr955: 14000800 Debug: 976 7708 riscv.c:3281 register_get(): [0]{0} read 0x14000800 from pmpaddr11 (valid=0) Debug: 977 7708 riscv.c:1484 riscv_start_algorithm(): save pmpaddr12 Debug: 978 7708 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr956 on hart 0 Debug: 979 7708 riscv-013.c:776 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc Debug: 980 7708 riscv-013.c:1426 register_read_direct(): {0} csr956 = 0x18000000 Debug: 981 7708 riscv.c:3005 riscv_get_register_on_hart(): {0} csr956: 18000000 Debug: 982 7708 riscv.c:3281 register_get(): [0]{0} read 0x18000000 from pmpaddr12 (valid=0) Debug: 983 7708 riscv.c:1484 riscv_start_algorithm(): save pmpaddr13 Debug: 984 7708 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr957 on hart 0 Debug: 985 7708 riscv-013.c:776 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 986 7709 riscv-013.c:1426 register_read_direct(): {0} csr957 = 0x18040000 Debug: 987 7709 riscv.c:3005 riscv_get_register_on_hart(): {0} csr957: 18040000 Debug: 988 7709 riscv.c:3281 register_get(): [0]{0} read 0x18040000 from pmpaddr13 (valid=0) Debug: 989 7709 riscv.c:1484 riscv_start_algorithm(): save pmpaddr14 Debug: 990 7709 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr958 on hart 0 Debug: 991 7709 riscv-013.c:776 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 992 7710 riscv-013.c:1426 register_read_direct(): {0} csr958 = 0x3fffffff Debug: 993 7710 riscv.c:3005 riscv_get_register_on_hart(): {0} csr958: 3fffffff Debug: 994 7710 riscv.c:3281 register_get(): [0]{0} read 0x3fffffff from pmpaddr14 (valid=0) Debug: 995 7710 riscv.c:1484 riscv_start_algorithm(): save pmpaddr15 Debug: 996 7710 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr959 on hart 0 Debug: 997 7710 riscv-013.c:776 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 998 7710 riscv-013.c:1426 register_read_direct(): {0} csr959 = 0x3fffffff Debug: 999 7710 riscv.c:3005 riscv_get_register_on_hart(): {0} csr959: 3fffffff Debug: 1000 7710 riscv.c:3281 register_get(): [0]{0} read 0x3fffffff from pmpaddr15 (valid=0) Debug: 1001 7710 riscv.c:1484 riscv_start_algorithm(): save tselect Debug: 1002 7710 riscv-013.c:3491 riscv013_get_register(): [0] reading register tselect on hart 0 Debug: 1003 7710 riscv-013.c:776 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 1004 7711 riscv-013.c:1426 register_read_direct(): {0} tselect = 0x0 Debug: 1005 7711 riscv.c:3005 riscv_get_register_on_hart(): {0} tselect: 0 Debug: 1006 7711 riscv.c:3281 register_get(): [0]{0} read 0x0 from tselect (valid=0) Debug: 1007 7711 riscv.c:1484 riscv_start_algorithm(): save tdata1 Debug: 1008 7711 riscv-013.c:3491 riscv013_get_register(): [0] reading register tdata1 on hart 0 Debug: 1009 7711 riscv-013.c:776 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 1010 7712 riscv-013.c:1426 register_read_direct(): {0} tdata1 = 0x23e00000 Debug: 1011 7712 riscv.c:3005 riscv_get_register_on_hart(): {0} tdata1: 23e00000 Debug: 1012 7712 riscv.c:3281 register_get(): [0]{0} read 0x23e00000 from tdata1 (valid=0) Debug: 1013 7712 riscv.c:1484 riscv_start_algorithm(): save tdata2 Debug: 1014 7712 riscv-013.c:3491 riscv013_get_register(): [0] reading register tdata2 on hart 0 Debug: 1015 7712 riscv-013.c:776 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 1016 7713 riscv-013.c:1426 register_read_direct(): {0} tdata2 = 0x0 Debug: 1017 7713 riscv.c:3005 riscv_get_register_on_hart(): {0} tdata2: 0 Debug: 1018 7713 riscv.c:3281 register_get(): [0]{0} read 0x0 from tdata2 (valid=0) Debug: 1019 7713 riscv.c:1484 riscv_start_algorithm(): save dcsr Debug: 1020 7713 riscv-013.c:3491 riscv013_get_register(): [0] reading register dcsr on hart 0 Debug: 1021 7713 riscv-013.c:776 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1022 7713 riscv-013.c:1426 register_read_direct(): {0} dcsr = 0xc3 Debug: 1023 7713 riscv.c:3005 riscv_get_register_on_hart(): {0} dcsr: c3 Debug: 1024 7713 riscv.c:3281 register_get(): [0]{0} read 0xc3 from dcsr (valid=0) Debug: 1025 7714 riscv.c:1484 riscv_start_algorithm(): save dpc Debug: 1026 7714 riscv-013.c:3491 riscv013_get_register(): [0] reading register dpc on hart 0 Debug: 1027 7714 riscv-013.c:776 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1028 7714 riscv-013.c:1426 register_read_direct(): {0} dpc = 0x4038a4ee Debug: 1029 7714 riscv.c:3005 riscv_get_register_on_hart(): {0} dpc: 4038a4ee Debug: 1030 7714 riscv.c:3281 register_get(): [0]{0} read 0x4038a4ee from dpc (valid=0) Debug: 1031 7714 riscv.c:1484 riscv_start_algorithm(): save dscratch Debug: 1032 7714 riscv-013.c:3491 riscv013_get_register(): [0] reading register dscratch on hart 0 Debug: 1033 7714 riscv-013.c:776 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 1034 7715 riscv-013.c:1426 register_read_direct(): {0} dscratch = 0x3fc9a2b0 Debug: 1035 7715 riscv.c:3005 riscv_get_register_on_hart(): {0} dscratch: 3fc9a2b0 Debug: 1036 7715 riscv.c:3281 register_get(): [0]{0} read 0x3fc9a2b0 from dscratch (valid=0) Debug: 1037 7715 riscv.c:1484 riscv_start_algorithm(): save mvendorid Debug: 1038 7715 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr3857 on hart 0 Debug: 1039 7715 riscv-013.c:776 execute_abstract_command(): command=0x220f11; access register, size=32, postexec=0, transfer=1, write=0, regno=0xf11 Debug: 1040 7716 riscv-013.c:1426 register_read_direct(): {0} csr3857 = 0x612 Debug: 1041 7716 riscv.c:3005 riscv_get_register_on_hart(): {0} csr3857: 612 Debug: 1042 7716 riscv.c:3281 register_get(): [0]{0} read 0x612 from mvendorid (valid=0) Debug: 1043 7716 riscv.c:1484 riscv_start_algorithm(): save marchid Debug: 1044 7716 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr3858 on hart 0 Debug: 1045 7716 riscv-013.c:776 execute_abstract_command(): command=0x220f12; access register, size=32, postexec=0, transfer=1, write=0, regno=0xf12 Debug: 1046 7717 riscv-013.c:1426 register_read_direct(): {0} csr3858 = 0x80000001 Debug: 1047 7717 riscv.c:3005 riscv_get_register_on_hart(): {0} csr3858: 80000001 Debug: 1048 7717 riscv.c:3281 register_get(): [0]{0} read 0x80000001 from marchid (valid=0) Debug: 1049 7717 riscv.c:1484 riscv_start_algorithm(): save mimpid Debug: 1050 7717 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr3859 on hart 0 Debug: 1051 7717 riscv-013.c:776 execute_abstract_command(): command=0x220f13; access register, size=32, postexec=0, transfer=1, write=0, regno=0xf13 Debug: 1052 7718 riscv-013.c:1426 register_read_direct(): {0} csr3859 = 0x1 Debug: 1053 7718 riscv.c:3005 riscv_get_register_on_hart(): {0} csr3859: 1 Debug: 1054 7718 riscv.c:3281 register_get(): [0]{0} read 0x1 from mimpid (valid=0) Debug: 1055 7718 riscv.c:1484 riscv_start_algorithm(): save mhartid Debug: 1056 7718 riscv-013.c:3491 riscv013_get_register(): [0] reading register csr3860 on hart 0 Debug: 1057 7718 riscv-013.c:776 execute_abstract_command(): command=0x220f14; access register, size=32, postexec=0, transfer=1, write=0, regno=0xf14 Debug: 1058 7718 riscv-013.c:1426 register_read_direct(): {0} csr3860 = 0x0 Debug: 1059 7718 riscv.c:3005 riscv_get_register_on_hart(): {0} csr3860: 0 Debug: 1060 7718 riscv.c:3281 register_get(): [0]{0} read 0x0 from mhartid (valid=0) Debug: 1061 7718 riscv.c:1484 riscv_start_algorithm(): save priv Debug: 1062 7718 riscv-013.c:3491 riscv013_get_register(): [0] reading register priv on hart 0 Debug: 1063 7718 riscv-013.c:776 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1064 7719 riscv-013.c:1426 register_read_direct(): {0} dcsr = 0x400000c3 Debug: 1065 7719 riscv.c:3005 riscv_get_register_on_hart(): {0} priv: 3 Debug: 1066 7719 riscv.c:3281 register_get(): [0]{0} read 0x3 from priv (valid=0) Debug: 1067 7719 riscv.c:1510 riscv_start_algorithm(): set sp Debug: 1068 7719 riscv.c:3294 register_set(): [0]{0} write 0x3fc84890 to sp (valid=1) Debug: 1069 7719 riscv.c:2966 riscv_set_register_on_hart(): {0} sp <- 3fc84890 Debug: 1070 7719 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x3fc84890 to register sp on hart 0 Debug: 1071 7719 riscv-013.c:1238 register_write_direct(): {0} sp <- 0x3fc84890 Debug: 1072 7719 riscv-013.c:776 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 1073 7720 riscv.c:1510 riscv_start_algorithm(): set a7 Debug: 1074 7720 riscv.c:3294 register_set(): [0]{0} write 0x403816d6 to a7 (valid=1) Debug: 1075 7720 riscv.c:2966 riscv_set_register_on_hart(): {0} a7 <- 403816d6 Debug: 1076 7720 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x403816d6 to register a7 on hart 0 Debug: 1077 7720 riscv-013.c:1238 register_write_direct(): {0} a7 <- 0x403816d6 Debug: 1078 7720 riscv-013.c:776 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 1079 7721 riscv.c:1510 riscv_start_algorithm(): set a0 Debug: 1080 7721 riscv.c:3294 register_set(): [0]{0} write 0x5 to a0 (valid=1) Debug: 1081 7721 riscv.c:2966 riscv_set_register_on_hart(): {0} a0 <- 5 Debug: 1082 7721 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x5 to register a0 on hart 0 Debug: 1083 7721 riscv-013.c:1238 register_write_direct(): {0} a0 <- 0x5 Debug: 1084 7721 riscv-013.c:776 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 1085 7721 riscv.c:1510 riscv_start_algorithm(): set a1 Debug: 1086 7721 riscv.c:3294 register_set(): [0]{0} write 0xffffffff to a1 (valid=1) Debug: 1087 7721 riscv.c:2966 riscv_set_register_on_hart(): {0} a1 <- ffffffff Debug: 1088 7721 riscv-013.c:3515 riscv013_set_register(): [0] writing 0xffffffff to register a1 on hart 0 Debug: 1089 7721 riscv-013.c:1238 register_write_direct(): {0} a1 <- 0xffffffff Debug: 1090 7722 riscv-013.c:776 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 1091 7722 riscv.c:1510 riscv_start_algorithm(): set a2 Debug: 1092 7722 riscv.c:3294 register_set(): [0]{0} write 0x3fc848ac to a2 (valid=1) Debug: 1093 7722 riscv.c:2966 riscv_set_register_on_hart(): {0} a2 <- 3fc848ac Debug: 1094 7722 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x3fc848ac to register a2 on hart 0 Debug: 1095 7722 riscv-013.c:1238 register_write_direct(): {0} a2 <- 0x3fc848ac Debug: 1096 7722 riscv-013.c:776 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 1097 7723 riscv.c:1569 riscv_interrupts_disable(): Disabling Interrupts Debug: 1098 7723 riscv-013.c:3491 riscv013_get_register(): [0] reading register mstatus on hart 0 Debug: 1099 7723 riscv-013.c:776 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 1100 7723 riscv-013.c:1426 register_read_direct(): {0} mstatus = 0x89 Debug: 1101 7723 riscv.c:3005 riscv_get_register_on_hart(): {0} mstatus: 89 Debug: 1102 7723 riscv.c:3281 register_get(): [0]{0} read 0x89 from mstatus (valid=0) Debug: 1103 7723 riscv.c:3294 register_set(): [0]{0} write 0x80 to mstatus (valid=0) Debug: 1104 7723 riscv.c:2966 riscv_set_register_on_hart(): {0} mstatus <- 80 Debug: 1105 7723 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x80 to register mstatus on hart 0 Debug: 1106 7723 riscv-013.c:1238 register_write_direct(): {0} mstatus <- 0x80 Debug: 1107 7724 riscv-013.c:776 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 1108 7724 riscv.c:1542 riscv_start_algorithm(): resume at 0x40381dd8 Debug: 1109 7724 riscv.c:1302 riscv_resume_internal(): handle_breakpoints=0 Debug: 1110 7724 riscv.c:1227 resume_prep(): [0] Debug: 1111 7724 riscv.c:2966 riscv_set_register_on_hart(): {0} pc <- 40381dd8 Debug: 1112 7724 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x40381dd8 to register pc on hart 0 Debug: 1113 7724 riscv-013.c:3523 riscv013_set_register(): [0] writing PC to DPC: 0x40381dd8 Debug: 1114 7724 riscv-013.c:1238 register_write_direct(): {0} dpc <- 0x40381dd8 Debug: 1115 7724 riscv-013.c:776 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 1116 7725 riscv-013.c:776 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1117 7726 riscv-013.c:1426 register_read_direct(): {0} dpc = 0x40381dd8 Debug: 1118 7726 riscv-013.c:3527 riscv013_set_register(): [0] actual DPC written: 0x0000000040381dd8 Debug: 1119 7726 riscv.c:1165 riscv_resume_prep_all_harts(): prep hart 0 Debug: 1120 7726 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 1121 7726 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100f @0 Debug: 1122 7726 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 1123 7726 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0xf @1 Debug: 1124 7726 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1125 7726 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1126 7726 riscv-013.c:776 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 1127 7727 program.c:33 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 1128 7727 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100f @0 Debug: 1129 7727 program.c:33 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 1130 7727 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0xf @1 Debug: 1131 7727 program.c:33 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1132 7727 riscv-013.c:3775 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1133 7727 riscv-013.c:776 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 1134 7727 riscv-013.c:776 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1135 7728 riscv-013.c:1426 register_read_direct(): {0} dcsr = 0x400000c3 Debug: 1136 7728 riscv.c:2966 riscv_set_register_on_hart(): {0} dcsr <- 4000b0c3 Debug: 1137 7728 riscv-013.c:3515 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr on hart 0 Debug: 1138 7728 riscv-013.c:1238 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 1139 7728 riscv-013.c:776 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 1140 7729 riscv.c:1176 riscv_resume_prep_all_harts(): [0] mark as prepped Debug: 1141 7729 riscv.c:1254 resume_prep(): [0] mark as prepped Debug: 1142 7729 riscv.c:2769 riscv_resume_go_all_harts(): resuming hart 0 Debug: 1143 7729 riscv-013.c:3588 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 1144 7729 riscv-013.c:4210 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0) Debug: 1145 7730 riscv.c:2909 riscv_invalidate_register_cache(): [0] Debug: 1146 7730 target.c:1636 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3 Debug: 1147 7730 algorithm.c:246 algorithm_run(): Wait algorithm completion Debug: 1148 7854 riscv.c:1824 riscv_poll_hart(): triggered a halt Debug: 1149 7854 riscv.c:1955 riscv_openocd_poll(): hart 0 halted Debug: 1150 7854 riscv-013.c:776 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1151 7855 riscv-013.c:799 execute_abstract_command(): command 0x2207b0 failed; abstractcs=0x10000302 Debug: 1152 7855 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1153 7856 riscv-013.c:799 execute_abstract_command(): command 0x221008 failed; abstractcs=0x10000302 Debug: 1154 7856 target.c:1636 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 1155 7856 target.c:1636 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 1156 7856 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable Debug: 1157 7856 command.c:143 script_debug(): command - command command mode Debug: 1158 7856 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1 Debug: 1159 7856 riscv.c:1828 riscv_poll_hart(): triggered running Debug: 1161 7857 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 1162 7858 command.c:143 script_debug(): command - mww mww 0x6001F048 0 Debug: 1164 7859 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 1165 7859 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1 Debug: 1166 7859 riscv.c:1824 riscv_poll_hart(): triggered a halt Debug: 1167 7859 riscv.c:1955 riscv_openocd_poll(): hart 0 halted Error: 1168 7860 riscv.c:3022 riscv_halt_reason(): Hart is not halted! Debug: 1169 7860 target.c:1636 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 1170 7860 target.c:1636 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 1171 7860 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable Debug: 1172 7860 command.c:143 script_debug(): command - command command mode Debug: 1173 7860 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1 Debug: 1175 7860 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 1176 7861 command.c:143 script_debug(): command - mww mww 0x6001F048 0 Debug: 1178 7861 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 1179 7862 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1 Debug: 1181 7862 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 1182 7863 command.c:143 script_debug(): command - mww mww 0x60020048 0 Debug: 1184 7864 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 1185 7864 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1 Debug: 1187 7864 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 1188 7865 command.c:143 script_debug(): command - mww mww 0x60008090 0 Debug: 1190 7866 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 1191 7866 command.c:143 script_debug(): command - mww mww 0x600080b0 0x8F1D312A Debug: 1193 7867 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 1194 7867 command.c:143 script_debug(): command - mww mww 0x600080ac 0x84B00000 Debug: 1196 7868 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 1198 7869 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 1199 7869 command.c:143 script_debug(): command - mww mww 0x60020048 0 Debug: 1200 7870 riscv.c:1828 riscv_poll_hart(): triggered running Debug: 1202 7870 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 1203 7870 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1 Debug: 1204 7871 riscv.c:1824 riscv_poll_hart(): triggered a halt Debug: 1205 7871 riscv.c:1955 riscv_openocd_poll(): hart 0 halted Debug: 1206 7871 riscv-013.c:776 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1207 7871 riscv-013.c:799 execute_abstract_command(): command 0x2207b0 failed; abstractcs=0x10000302 Debug: 1208 7872 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1209 7872 riscv-013.c:799 execute_abstract_command(): command 0x221008 failed; abstractcs=0x10000302 Debug: 1210 7872 target.c:1636 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 1211 7872 target.c:1636 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 1212 7872 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable Debug: 1213 7872 command.c:143 script_debug(): command - command command mode Debug: 1214 7872 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1 Debug: 1216 7873 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 1217 7873 command.c:143 script_debug(): command - mww mww 0x6001F048 0 Debug: 1219 7874 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 1220 7874 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1 Debug: 1222 7875 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 1223 7875 command.c:143 script_debug(): command - mww mww 0x60020048 0 Debug: 1225 7876 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 1226 7876 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1 Debug: 1228 7876 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 1229 7877 command.c:143 script_debug(): command - mww mww 0x60008090 0 Debug: 1231 7877 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 1232 7878 command.c:143 script_debug(): command - mww mww 0x600080b0 0x8F1D312A Debug: 1234 7878 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 1235 7879 command.c:143 script_debug(): command - mww mww 0x600080ac 0x84B00000 Debug: 1237 7879 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 1239 7880 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 1240 7881 command.c:143 script_debug(): command - mww mww 0x60008090 0 Debug: 1241 7881 riscv.c:1828 riscv_poll_hart(): triggered running Debug: 1243 7882 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 1244 7882 command.c:143 script_debug(): command - mww mww 0x600080b0 0x8F1D312A Debug: 1245 7882 riscv.c:1824 riscv_poll_hart(): triggered a halt Debug: 1246 7882 riscv.c:1955 riscv_openocd_poll(): hart 0 halted Debug: 1247 7883 riscv-013.c:776 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 1248 7883 riscv-013.c:799 execute_abstract_command(): command 0x2207b0 failed; abstractcs=0x10000302 Debug: 1249 7883 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1250 7884 riscv-013.c:799 execute_abstract_command(): command 0x221008 failed; abstractcs=0x10000302 Debug: 1251 7884 target.c:1636 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 1252 7884 target.c:1636 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 1253 7884 target.c:4633 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable Debug: 1254 7884 command.c:143 script_debug(): command - command command mode Debug: 1255 7884 command.c:143 script_debug(): command - mww mww 0x6001f064 0x50D83AA1 Debug: 1257 7885 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 1258 7885 command.c:143 script_debug(): command - mww mww 0x6001F048 0 Debug: 1260 7886 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 1261 7886 command.c:143 script_debug(): command - mww mww 0x60020064 0x50D83AA1 Debug: 1263 7886 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 1264 7887 command.c:143 script_debug(): command - mww mww 0x60020048 0 Debug: 1266 7887 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 1267 7888 command.c:143 script_debug(): command - mww mww 0x600080a8 0x50D83AA1 Debug: 1269 7888 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 1270 7889 command.c:143 script_debug(): command - mww mww 0x60008090 0 Debug: 1272 7889 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 1273 7890 command.c:143 script_debug(): command - mww mww 0x600080b0 0x8F1D312A Debug: 1275 7890 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 1276 7890 command.c:143 script_debug(): command - mww mww 0x600080ac 0x84B00000 Debug: 1278 7891 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 1280 7892 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 1281 7892 command.c:143 script_debug(): command - mww mww 0x600080ac 0x84B00000 Debug: 1283 7893 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 1284 7893 riscv-013.c:3491 riscv013_get_register(): [0] reading register pc on hart 0 Debug: 1285 7893 riscv-013.c:776 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1286 7894 riscv-013.c:799 execute_abstract_command(): command 0x2207b1 failed; abstractcs=0x10000302 Debug: 1287 7894 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1288 7895 riscv-013.c:799 execute_abstract_command(): command 0x221008 failed; abstractcs=0x10000302 Debug: 1289 7895 riscv-013.c:3499 riscv013_get_register(): [0] read PC from DPC: 0x17caa431747 Debug: 1290 7895 riscv.c:3005 riscv_get_register_on_hart(): {0} pc: 17caa431747 Error: 1291 7895 algorithm.c:253 algorithm_run(): Failed to wait algorithm (-4)! Error: 1292 7895 algorithm.c:272 algorithm_run(): Algorithm run failed (-4)! Debug: 1293 7896 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc848ac Debug: 1294 7897 target.c:1978 target_free_working_area_restore(): freed 28 bytes of working area at address 0x3fc848ac Debug: 1295 7897 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 1296 7897 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 1297 7897 target.c:1751 print_wa_layout(): 0x3fc848ac-0x3fca3fff (128852 bytes) Error: 1298 7897 esp_flash.c:377 esp_flash_get_mappings(): Failed to run flasher stub (-4)! Warn : 1299 7897 esp_flash.c:927 esp_flash_probe(): Failed to get flash mappings (-4)! Debug: 1300 7897 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 1301 7897 algorithm.c:336 algorithm_load_func_image(): stub: base 0x0, start 0x403816d6, 2 sections Debug: 1302 7897 algorithm.c:344 algorithm_load_func_image(): addr 0x00000000, sz 7640, flags 1 Debug: 1303 7897 target.c:1890 alloc_working_area_try_do(): allocated new working area of 7640 bytes at address 0x40381ddc Debug: 1304 7897 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:1910 start address: 0x40381ddc Debug: 1305 7897 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381ddc Debug: 1306 7898 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381e5c Debug: 1307 7899 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381edc Debug: 1308 7900 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381f5c Debug: 1309 7902 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381fdc Debug: 1310 7903 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038205c Debug: 1311 7904 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403820dc Debug: 1313 7905 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038215c Debug: 1314 7906 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403821dc Debug: 1315 7907 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038225c Debug: 1316 7908 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403822dc Debug: 1317 7909 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038235c Debug: 1318 7910 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403823dc Debug: 1319 7911 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038245c Debug: 1320 7912 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403824dc Debug: 1321 7913 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038255c Debug: 1322 7914 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403825dc Debug: 1323 7916 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038265c Debug: 1324 7917 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403826dc Debug: 1325 7918 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038275c Debug: 1326 7919 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403827dc Debug: 1327 7920 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038285c Debug: 1328 7921 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403828dc Debug: 1329 7922 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038295c Debug: 1330 7923 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403829dc Debug: 1331 7924 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382a5c Debug: 1332 7925 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382adc Debug: 1333 7926 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382b5c Debug: 1334 7927 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382bdc Debug: 1335 7929 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382c5c Debug: 1336 7930 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382cdc Debug: 1337 7931 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382d5c Debug: 1338 7932 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382ddc Debug: 1339 7933 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382e5c Debug: 1340 7934 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382edc Debug: 1341 7935 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382f5c Debug: 1342 7936 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382fdc Debug: 1343 7937 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038305c Debug: 1344 7939 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403830dc Debug: 1345 7940 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038315c Debug: 1346 7941 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403831dc Debug: 1347 7942 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038325c Debug: 1348 7943 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403832dc Debug: 1349 7944 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038335c Debug: 1350 7945 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403833dc Debug: 1351 7946 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038345c Debug: 1352 7948 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403834dc Debug: 1353 7949 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038355c Debug: 1354 7950 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403835dc Debug: 1355 7951 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038365c Debug: 1356 7952 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403836dc Debug: 1357 7953 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038375c Debug: 1358 7954 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403837dc Debug: 1359 7955 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038385c Debug: 1360 7956 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403838dc Debug: 1361 7957 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038395c Debug: 1362 7958 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403839dc Debug: 1363 7959 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40383a5c Debug: 1364 7960 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40383adc Debug: 1365 7961 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40383b5c Debug: 1366 7962 target.c:1751 print_wa_layout(): b 0x40380000-0x40381dd7 (7640 bytes) Debug: 1367 7962 target.c:1751 print_wa_layout(): b 0x40381dd8-0x40381ddb (4 bytes) Debug: 1368 7962 target.c:1751 print_wa_layout(): b* 0x40381ddc-0x40383bb3 (7640 bytes) Debug: 1369 7962 target.c:1751 print_wa_layout(): 0x40383bb4-0x40383fff (1100 bytes) Debug: 1370 7962 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381ddc Debug: 1371 7963 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381ddc Debug: 1372 7965 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381e5c Debug: 1373 7967 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381edc Debug: 1374 7969 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381f5c Debug: 1375 7971 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381fdc Debug: 1376 7971 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381fdc Debug: 1377 7973 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038205c Debug: 1378 7975 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403820dc Debug: 1379 7977 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038215c Debug: 1380 7978 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403821dc Debug: 1381 7979 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403821dc Debug: 1382 7981 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038225c Debug: 1383 7983 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403822dc Debug: 1384 7985 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038235c Debug: 1385 7986 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403823dc Debug: 1386 7987 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403823dc Debug: 1387 7989 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038245c Debug: 1388 7990 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403824dc Debug: 1389 7992 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038255c Debug: 1390 7994 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403825dc Debug: 1391 7994 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403825dc Debug: 1392 7996 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038265c Debug: 1393 7997 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403826dc Debug: 1394 7999 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038275c Debug: 1395 8001 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403827dc Debug: 1396 8002 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403827dc Debug: 1397 8003 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038285c Debug: 1398 8005 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403828dc Debug: 1399 8007 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038295c Debug: 1400 8009 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403829dc Debug: 1401 8009 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403829dc Debug: 1402 8011 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382a5c Debug: 1403 8013 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382adc Debug: 1404 8014 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382b5c Debug: 1405 8016 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40382bdc Debug: 1406 8017 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382bdc Debug: 1407 8018 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382c5c Debug: 1408 8020 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382cdc Debug: 1409 8022 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382d5c Debug: 1410 8024 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40382ddc Debug: 1411 8024 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382ddc Debug: 1412 8026 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382e5c Debug: 1413 8028 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382edc Debug: 1414 8030 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382f5c Debug: 1415 8031 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40382fdc Debug: 1416 8032 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382fdc Debug: 1417 8033 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038305c Debug: 1418 8035 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403830dc Debug: 1419 8037 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038315c Debug: 1420 8039 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403831dc Debug: 1421 8040 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403831dc Debug: 1422 8041 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038325c Debug: 1423 8043 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403832dc Debug: 1424 8045 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038335c Debug: 1425 8047 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403833dc Debug: 1426 8047 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403833dc Debug: 1427 8049 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038345c Debug: 1428 8051 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403834dc Debug: 1429 8053 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038355c Debug: 1430 8055 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403835dc Debug: 1431 8055 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403835dc Debug: 1432 8057 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038365c Debug: 1433 8059 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403836dc Debug: 1434 8061 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038375c Debug: 1435 8062 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403837dc Debug: 1436 8063 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403837dc Debug: 1437 8064 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038385c Debug: 1438 8067 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403838dc Debug: 1439 8069 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038395c Debug: 1440 8071 target.c:2237 target_write_buffer(): writing buffer of 472 byte at 0x403839dc Debug: 1441 8073 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403839dc Debug: 1442 8078 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383a5c Debug: 1443 8080 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383adc Debug: 1444 8084 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383b5c Debug: 1445 8086 algorithm.c:344 algorithm_load_func_image(): addr 0x00000000, sz 637, flags 0 Debug: 1446 8086 target.c:1890 alloc_working_area_try_do(): allocated new working area of 920 bytes at address 0x3fc848ac Debug: 1447 8086 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:230 start address: 0x3fc848ac Debug: 1448 8088 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc848ac Debug: 1449 8090 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc8492c Debug: 1450 8092 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc849ac Debug: 1451 8094 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84a2c Debug: 1452 8096 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84aac Debug: 1453 8098 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84b2c Debug: 1454 8099 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84bac Debug: 1455 8101 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84c2c Debug: 1456 8101 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 1457 8101 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 1458 8101 target.c:1751 print_wa_layout(): b 0x3fc848ac-0x3fc84c43 (920 bytes) Debug: 1459 8101 target.c:1751 print_wa_layout(): 0x3fc84c44-0x3fca3fff (127932 bytes) Debug: 1460 8101 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x3fc848ac Debug: 1461 8102 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc848ac Debug: 1462 8105 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc8492c Debug: 1463 8108 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc849ac Debug: 1464 8111 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84a2c Debug: 1465 8114 target.c:2237 target_write_buffer(): writing buffer of 125 byte at 0x3fc84aac Debug: 1466 8115 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84aac Debug: 1467 8117 riscv-013.c:3226 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc84b28 Debug: 1468 8117 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1469 8118 riscv-013.c:799 execute_abstract_command(): command 0x221008 failed; abstractcs=0x10000302 Error: 1470 8118 algorithm.c:417 algorithm_load_func_image(): Failed to write stub section! Debug: 1471 8119 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381ddc Debug: 1472 8122 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381e5c Debug: 1473 8125 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381edc Debug: 1474 8128 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381f5c Debug: 1475 8130 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381fdc Debug: 1476 8133 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038205c Debug: 1477 8135 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403820dc Debug: 1478 8137 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038215c Debug: 1479 8140 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403821dc Debug: 1480 8144 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038225c Debug: 1481 8147 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403822dc Debug: 1482 8149 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038235c Debug: 1483 8152 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403823dc Debug: 1484 8155 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038245c Debug: 1485 8158 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403824dc Debug: 1486 8161 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038255c Debug: 1487 8163 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403825dc Debug: 1488 8165 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038265c Debug: 1489 8168 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403826dc Debug: 1490 8171 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038275c Debug: 1491 8174 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403827dc Debug: 1492 8176 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038285c Debug: 1493 8179 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403828dc Debug: 1494 8181 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038295c Debug: 1495 8184 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403829dc Debug: 1496 8187 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382a5c Debug: 1497 8189 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382adc Debug: 1498 8192 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382b5c Debug: 1499 8195 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382bdc Debug: 1500 8197 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382c5c Debug: 1501 8200 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382cdc Debug: 1502 8202 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382d5c Debug: 1503 8205 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382ddc Debug: 1504 8208 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382e5c Debug: 1505 8210 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382edc Debug: 1506 8213 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382f5c Debug: 1507 8216 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382fdc Debug: 1508 8218 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038305c Debug: 1509 8221 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403830dc Debug: 1510 8223 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038315c Debug: 1511 8225 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403831dc Debug: 1512 8228 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038325c Debug: 1513 8231 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403832dc Debug: 1514 8233 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038335c Debug: 1515 8236 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403833dc Debug: 1516 8239 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038345c Debug: 1517 8242 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403834dc Debug: 1518 8245 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038355c Debug: 1519 8248 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403835dc Debug: 1520 8251 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038365c Debug: 1521 8254 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403836dc Debug: 1522 8257 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038375c Debug: 1523 8259 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403837dc Debug: 1524 8261 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038385c Debug: 1525 8264 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403838dc Debug: 1526 8266 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038395c Debug: 1527 8269 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403839dc Debug: 1528 8272 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383a5c Debug: 1529 8275 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383adc Debug: 1530 8278 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383b5c Debug: 1531 8280 target.c:1978 target_free_working_area_restore(): freed 7640 bytes of working area at address 0x40381ddc Debug: 1532 8280 target.c:1751 print_wa_layout(): b 0x40380000-0x40381dd7 (7640 bytes) Debug: 1533 8280 target.c:1751 print_wa_layout(): b 0x40381dd8-0x40381ddb (4 bytes) Debug: 1534 8280 target.c:1751 print_wa_layout(): 0x40381ddc-0x40383fff (8740 bytes) Debug: 1535 8281 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc848ac Debug: 1536 8284 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc8492c Debug: 1537 8287 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc849ac Debug: 1538 8290 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84a2c Debug: 1539 8293 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84aac Debug: 1540 8295 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84b2c Debug: 1541 8298 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84bac Debug: 1542 8300 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84c2c Debug: 1543 8301 target.c:1978 target_free_working_area_restore(): freed 920 bytes of working area at address 0x3fc848ac Debug: 1544 8301 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 1545 8301 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 1546 8301 target.c:1751 print_wa_layout(): 0x3fc848ac-0x3fca3fff (128852 bytes) Error: 1547 8301 esp_flash.c:339 esp_flash_get_size(): Failed to run flasher stub (-4)! Debug: 1548 8301 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 1549 8301 algorithm.c:336 algorithm_load_func_image(): stub: base 0x0, start 0x403816d6, 2 sections Debug: 1550 8301 algorithm.c:344 algorithm_load_func_image(): addr 0x00000000, sz 7640, flags 1 Debug: 1551 8301 target.c:1890 alloc_working_area_try_do(): allocated new working area of 7640 bytes at address 0x40381ddc Debug: 1552 8301 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:1910 start address: 0x40381ddc Debug: 1553 8302 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381ddc Debug: 1554 8304 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381e5c Debug: 1555 8307 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381edc Debug: 1556 8308 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381f5c Debug: 1557 8311 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40381fdc Debug: 1558 8313 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038205c Debug: 1559 8316 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403820dc Debug: 1560 8318 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038215c Debug: 1561 8320 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403821dc Debug: 1562 8322 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038225c Debug: 1563 8324 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403822dc Debug: 1564 8326 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038235c Debug: 1565 8328 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403823dc Debug: 1566 8330 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038245c Debug: 1567 8331 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403824dc Debug: 1568 8333 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038255c Debug: 1569 8335 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403825dc Debug: 1570 8337 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038265c Debug: 1571 8340 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403826dc Debug: 1572 8342 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038275c Debug: 1573 8344 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403827dc Debug: 1574 8347 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038285c Debug: 1575 8348 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403828dc Debug: 1576 8350 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038295c Debug: 1577 8352 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403829dc Debug: 1578 8354 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382a5c Debug: 1579 8356 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382adc Debug: 1580 8358 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382b5c Debug: 1581 8360 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382bdc Debug: 1582 8362 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382c5c Debug: 1583 8363 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382cdc Debug: 1584 8366 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382d5c Debug: 1585 8368 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382ddc Debug: 1586 8370 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382e5c Debug: 1587 8372 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382edc Debug: 1588 8374 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382f5c Debug: 1589 8376 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40382fdc Debug: 1590 8378 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038305c Debug: 1591 8380 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403830dc Debug: 1592 8382 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038315c Debug: 1593 8384 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403831dc Debug: 1594 8386 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038325c Debug: 1595 8388 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403832dc Debug: 1596 8390 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038335c Debug: 1597 8392 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403833dc Debug: 1598 8393 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038345c Debug: 1599 8395 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403834dc Debug: 1600 8397 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038355c Debug: 1601 8399 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403835dc Debug: 1602 8401 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038365c Debug: 1603 8403 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403836dc Debug: 1604 8405 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038375c Debug: 1606 8407 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403837dc Debug: 1607 8409 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038385c Debug: 1608 8412 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403838dc Debug: 1609 8414 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x4038395c Debug: 1610 8416 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x403839dc Debug: 1611 8418 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40383a5c Debug: 1612 8420 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40383adc Debug: 1613 8422 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x40383b5c Debug: 1614 8423 target.c:1751 print_wa_layout(): b 0x40380000-0x40381dd7 (7640 bytes) Debug: 1615 8423 target.c:1751 print_wa_layout(): b 0x40381dd8-0x40381ddb (4 bytes) Debug: 1616 8423 target.c:1751 print_wa_layout(): b 0x40381ddc-0x40383bb3 (7640 bytes) Debug: 1617 8423 target.c:1751 print_wa_layout(): 0x40383bb4-0x40383fff (1100 bytes) Debug: 1618 8423 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381ddc Debug: 1619 8424 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381ddc Debug: 1620 8426 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381e5c Debug: 1621 8429 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381edc Debug: 1622 8431 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381f5c Debug: 1623 8434 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40381fdc Debug: 1624 8435 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381fdc Debug: 1625 8437 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038205c Debug: 1626 8440 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403820dc Debug: 1627 8443 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038215c Debug: 1628 8447 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403821dc Debug: 1629 8448 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403821dc Debug: 1630 8451 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038225c Debug: 1631 8454 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403822dc Debug: 1632 8457 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038235c Debug: 1633 8460 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403823dc Debug: 1634 8461 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403823dc Debug: 1635 8464 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038245c Debug: 1636 8467 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403824dc Debug: 1637 8470 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038255c Debug: 1638 8472 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403825dc Debug: 1639 8473 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403825dc Debug: 1640 8476 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038265c Debug: 1641 8479 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403826dc Debug: 1642 8483 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038275c Debug: 1643 8486 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403827dc Debug: 1644 8487 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403827dc Debug: 1645 8490 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038285c Debug: 1646 8493 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403828dc Debug: 1647 8496 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038295c Debug: 1648 8499 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403829dc Debug: 1649 8500 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403829dc Debug: 1650 8503 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382a5c Debug: 1651 8506 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382adc Debug: 1652 8509 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382b5c Debug: 1653 8512 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40382bdc Debug: 1654 8514 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382bdc Debug: 1655 8517 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382c5c Debug: 1656 8519 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382cdc Debug: 1657 8522 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382d5c Debug: 1658 8526 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40382ddc Debug: 1659 8527 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382ddc Debug: 1660 8529 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382e5c Debug: 1661 8533 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382edc Debug: 1662 8536 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382f5c Debug: 1663 8539 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x40382fdc Debug: 1664 8540 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382fdc Debug: 1665 8543 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038305c Debug: 1666 8547 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403830dc Debug: 1667 8550 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038315c Debug: 1668 8552 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403831dc Debug: 1669 8554 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403831dc Debug: 1670 8557 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038325c Debug: 1671 8560 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403832dc Debug: 1672 8563 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038335c Debug: 1673 8566 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403833dc Debug: 1674 8567 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403833dc Debug: 1675 8570 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038345c Debug: 1676 8574 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403834dc Debug: 1677 8577 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038355c Debug: 1678 8580 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403835dc Debug: 1679 8581 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403835dc Debug: 1680 8584 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038365c Debug: 1681 8587 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403836dc Debug: 1682 8589 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038375c Debug: 1683 8593 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x403837dc Debug: 1684 8594 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403837dc Debug: 1685 8597 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038385c Debug: 1686 8600 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403838dc Debug: 1687 8603 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038395c Debug: 1688 8607 target.c:2237 target_write_buffer(): writing buffer of 472 byte at 0x403839dc Debug: 1689 8608 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403839dc Debug: 1690 8611 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383a5c Debug: 1691 8614 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383adc Debug: 1692 8617 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383b5c Debug: 1693 8618 algorithm.c:344 algorithm_load_func_image(): addr 0x00000000, sz 637, flags 0 Debug: 1694 8618 target.c:1890 alloc_working_area_try_do(): allocated new working area of 920 bytes at address 0x3fc848ac Debug: 1695 8618 riscv-013.c:2311 read_memory_bus_v1(): System Bus Access: size: 4 count:230 start address: 0x3fc848ac Debug: 1696 8619 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc848ac Debug: 1697 8622 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc8492c Debug: 1698 8624 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc849ac Debug: 1699 8626 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84a2c Debug: 1700 8628 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84aac Debug: 1701 8629 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84b2c Debug: 1702 8632 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84bac Debug: 1703 8634 riscv-013.c:2326 read_memory_bus_v1(): reading burst starting at address 0x3fc84c2c Debug: 1704 8634 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 1705 8634 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 1706 8634 target.c:1751 print_wa_layout(): b* 0x3fc848ac-0x3fc84c43 (920 bytes) Debug: 1707 8634 target.c:1751 print_wa_layout(): 0x3fc84c44-0x3fca3fff (127932 bytes) Debug: 1708 8634 target.c:2237 target_write_buffer(): writing buffer of 512 byte at 0x3fc848ac Debug: 1709 8636 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc848ac Debug: 1710 8638 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc8492c Debug: 1711 8641 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc849ac Debug: 1712 8644 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84a2c Debug: 1713 8647 target.c:2237 target_write_buffer(): writing buffer of 125 byte at 0x3fc84aac Debug: 1714 8648 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84aac Debug: 1715 8651 riscv-013.c:3226 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc84b28 Debug: 1716 8651 riscv-013.c:776 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Error: 1717 13661 riscv-013.c:757 wait_for_idle(): Abstract command ended in error 'exception' (abstractcs=0x10001302) Error: 1718 13661 riscv-013.c:761 wait_for_idle(): Timed out after 5s waiting for busy to go low (abstractcs=0x10001302). Increase the timeout with riscv set_command_timeout_sec. Debug: 1719 13661 riscv-013.c:799 execute_abstract_command(): command 0x221008 failed; abstractcs=0x10001302 Error: 1720 13661 algorithm.c:417 algorithm_load_func_image(): Failed to write stub section! Debug: 1721 13662 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381ddc Debug: 1722 13662 log.c:406 keep_alive(): keep_alive() was not invoked in the 1000ms timelimit (5257). This may cause trouble with GDB connections. Debug: 1724 13663 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381e5c Debug: 1725 13664 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381edc Debug: 1726 13666 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381f5c Debug: 1727 13667 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40381fdc Debug: 1728 13669 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038205c Debug: 1729 13670 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403820dc Debug: 1730 13672 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038215c Debug: 1731 13673 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403821dc Debug: 1732 13674 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038225c Debug: 1733 13676 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403822dc Debug: 1734 13677 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038235c Debug: 1735 13678 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403823dc Debug: 1736 13680 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038245c Debug: 1737 13681 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403824dc Debug: 1738 13683 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038255c Debug: 1739 13684 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403825dc Debug: 1740 13685 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038265c Debug: 1741 13687 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403826dc Debug: 1742 13688 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038275c Debug: 1743 13689 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403827dc Debug: 1744 13691 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038285c Debug: 1745 13692 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403828dc Debug: 1746 13693 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038295c Debug: 1747 13695 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403829dc Debug: 1748 13696 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382a5c Debug: 1749 13698 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382adc Debug: 1750 13699 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382b5c Debug: 1751 13700 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382bdc Debug: 1752 13702 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382c5c Debug: 1753 13704 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382cdc Debug: 1754 13705 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382d5c Debug: 1755 13706 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382ddc Debug: 1756 13708 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382e5c Debug: 1757 13709 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382edc Debug: 1758 13710 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382f5c Debug: 1759 13712 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40382fdc Debug: 1760 13713 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038305c Debug: 1761 13715 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403830dc Debug: 1762 13716 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038315c Debug: 1763 13718 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403831dc Debug: 1764 13719 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038325c Debug: 1765 13720 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403832dc Debug: 1766 13721 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038335c Debug: 1767 13723 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403833dc Debug: 1768 13724 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038345c Debug: 1769 13725 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403834dc Debug: 1770 13727 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038355c Debug: 1771 13728 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403835dc Debug: 1772 13730 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038365c Debug: 1773 13731 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403836dc Debug: 1774 13732 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038375c Debug: 1775 13734 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403837dc Debug: 1776 13735 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038385c Debug: 1777 13737 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403838dc Debug: 1778 13738 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x4038395c Debug: 1779 13740 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x403839dc Debug: 1780 13741 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383a5c Debug: 1781 13743 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383adc Debug: 1782 13744 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x40383b5c Debug: 1783 13745 target.c:1978 target_free_working_area_restore(): freed 7640 bytes of working area at address 0x40381ddc Debug: 1784 13745 target.c:1751 print_wa_layout(): b 0x40380000-0x40381dd7 (7640 bytes) Debug: 1785 13745 target.c:1751 print_wa_layout(): b 0x40381dd8-0x40381ddb (4 bytes) Debug: 1786 13745 target.c:1751 print_wa_layout(): 0x40381ddc-0x40383fff (8740 bytes) Debug: 1787 13745 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc848ac Debug: 1788 13747 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc8492c Debug: 1789 13748 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc849ac Debug: 1790 13749 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84a2c Debug: 1791 13750 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84aac Debug: 1792 13752 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84b2c Debug: 1793 13753 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84bac Debug: 1794 13754 riscv-013.c:3118 write_memory_bus_v1(): transferring burst starting at address 0x3fc84c2c Debug: 1795 13755 target.c:1978 target_free_working_area_restore(): freed 920 bytes of working area at address 0x3fc848ac Debug: 1796 13755 target.c:1751 print_wa_layout(): b 0x3fc84000-0x3fc84397 (920 bytes) Debug: 1797 13755 target.c:1751 print_wa_layout(): b 0x3fc84398-0x3fc848ab (1300 bytes) Debug: 1798 13755 target.c:1751 print_wa_layout(): 0x3fc848ac-0x3fca3fff (128852 bytes) Error: 1799 13755 esp_flash.c:339 esp_flash_get_size(): Failed to run flasher stub (-4)! Error: 1800 13755 esp_flash.c:967 esp_flash_probe(): Failed to probe flash, size 0 KB Error: 1801 13755 core.c:263 get_flash_bank_by_num(): auto_probe failed Error: 1802 13755 gdb_server.c:1002 gdb_new_connection(): Connect failed. Consider setting up a gdb-attach event for the target to prepare target for GDB connect, or use 'gdb_memory_map disable'. Error: 1803 13755 server.c:104 add_connection(): attempted 'gdb' connection rejected

jonsmirl commented 2 years ago

I have this module, maybe they have used a flash chip you weren't expecting? ESP-C3-12F https://www.waveshare.com/w/upload/4/46/Nodemcu-esp-c3-32s-kit-schematics.pdf

gerekon commented 2 years ago

@jonsmirl This happens due to enable memory protection. You have two options: 1) Disable it in project's menuconfig. 2) Reset chip between OpenOCD and GDB start.

In the next release OpenOCD will do reset itself if memory protection is enabled.

jonsmirl commented 2 years ago

This explains why it would sometimes work and sometimes fail, it was a function of me randomly resetting without being aware that the manual reset was required. This is very non-obvious.

Please add a bug comment when you have the code checked in and I will test it. I would also recommend a debug message that is explicit about memory protection and inability to write to memory.

jonsmirl commented 2 years ago

Isn't there a way for the JTAG to turn memory protection on/off without a reset? Normally you would want to leave memory protected at all times. Then if JTAG needs to modify: turn protection off, modify, turn it back on.

igrr commented 2 years ago

@jonsmirl In ESP32-S2 and later, memory protection peripheral has a "lock" feature. Memory protection configuration can be locked by software, preventing further changes. This is a security measure to prevent features such as no-execute protection and code protection from being disabled due to some code vulnerabilities. After the configuration is locked, it can only be changed on CPU reset.

The change we will implement in OpenOCD is to detect that memory protection is locked, and reset the target if so.

Note that disabling memory protection doesn't disable RISC-V PMP or Xtensa region protection. So exceptions on access to illegal addresses will still be generated. The only protections which are disabled are:

Overall with memory protection disabled you should get very similar debugging experience, as these protections are unlikely to be triggered by typical programming errors.

jonsmirl commented 2 years ago

If would be good to turn protection off/on around this one: preventing code in IRAM from being overwritten — disabled to allow placing breakpoints Wild pointer writes more likely to hit code than data since there is usually more code to hit.

For sure keep first 1K of memory protected, by far most invalid accesses occur in that range. NULL pointer and offset from NULL pointer for structure member.

My target system is ESP32-C3.

chuanjinpang commented 2 years ago

it's same bug OCD-402. esp32c3 GDB can't connect openocd successful with USB build-in jtag if do hard reset after flash (OCD-402) #176

jonsmirl commented 2 years ago

This is working for me now that I know about the need for reset.

When you encounter this there is no clue given that reset will fix it. I spent a couple weeks frustrated by the JTAG working sometimes and then failing on the next run. I was not able to correlate the success or failure of JTAG with pressing the reset button until I was told. If openocd has simply printed out "reset needed to clear lock bit" I would not have wasted so much time on this.

chuanjinpang commented 2 years ago

This is working for me now that I know about the need for reset.

When you encounter this there is no clue given that reset will fix it. I spent a couple weeks frustrated by the JTAG working sometimes and then failing on the next run. I was not able to correlate the success or failure of JTAG with pressing the reset button until I was told. If openocd has simply printed out "reset needed to clear lock bit" I would not have wasted so much time on this.

yes, it's also cost me several days to debug this issue. it easy find isse should fix in espressif RD stage.