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OpenOCD branch with ESP32 JTAG support
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ESP32C3 - USB openocd - Hart 0 unexpectedly reset (OCD-475) #209

Closed andrew-elder closed 8 months ago

andrew-elder commented 2 years ago

Development Kit

ESP32-C3-DevKitM-1

Module or chip used

ESP32-C3-MINI-1 module

Debug Adapter

USB D+/D- connection

OpenOCD version

v0.11.0-esp32-20211220 (2021-12-20-15:42)

Operating System

Linux

Using an IDE ?

No, used command line

OpenOCD command line

$ openocd -f board/esp32c3-builtin.cfg

JTAG Clock Speed

40000 kHz

ESP-IDF version

v4.4

Problem Description

I have moved R1 -> R2 and then R4 -> R3 so that the USB cable connects directly to USB_DN and USB_DP.

I am running on a Linux virtual machine (VMware) that is running on a Windows host.

This is what I get

$ openocd -f board/esp32c3-builtin.cfg
Open On-Chip Debugger  v0.11.0-esp32-20211220 (2021-12-20-15:42)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Info : esp_usb_jtag: capabilities descriptor set to 0x2000
Warn : Transport "jtag" was already selected
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255
Info : clock speed 40000 kHz
Info : JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=32, misa=0x40101104
Info : Hart 0 unexpectedly reset
Info : starting gdb server for esp32c3 on 3333
Info : Listening on port 3333 for gdb connections
Info : Hart 0 unexpectedly reset
Info : Hart 0 unexpectedly reset
Info : Hart 0 unexpectedly reset
Info : Hart 0 unexpectedly reset
....

Debug Logs

Verbose log follows

Debug: 17 1 log.c:251 handle_log_output_command(): set log_output to "openocd_log.txt"
Debug: 18 1 options.c:244 add_default_dirs(): bindir=/builds/idf/openocd-esp32/_build/../openocd-esp32/bin
Debug: 19 1 options.c:245 add_default_dirs(): pkgdatadir=/builds/idf/openocd-esp32/_build/../openocd-esp32/share/openocd
Debug: 20 1 options.c:246 add_default_dirs(): exepath=/home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/bin
Debug: 21 1 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 22 1 configuration.c:42 add_script_search_dir(): adding /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts
Debug: 23 1 configuration.c:42 add_script_search_dir(): adding /home/logix/.config/openocd
Debug: 24 1 configuration.c:42 add_script_search_dir(): adding /home/logix/.openocd
Debug: 25 1 configuration.c:42 add_script_search_dir(): adding /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/bin/../share/openocd/site
Debug: 26 1 configuration.c:42 add_script_search_dir(): adding /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/bin/../share/openocd/scripts
Debug: 27 1 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/board/esp32c3-builtin.cfg
Debug: 28 1 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/interface/esp_usb_jtag.cfg
Debug: 29 1 command.c:146 script_debug(): command - adapter driver esp_usb_jtag
Info : 31 1 transport.c:117 allow_transports(): only one transport option; autoselect 'jtag'
Debug: 32 2 command.c:146 script_debug(): command - espusbjtag vid_pid 0x303a 0x1001
Info : 34 2 esp_usb_jtag.c:899 esp_usb_jtag_vid_pid(): esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Debug: 35 2 command.c:146 script_debug(): command - espusbjtag caps_descriptor 0x2000
Info : 37 2 esp_usb_jtag.c:912 esp_usb_jtag_caps_descriptor(): esp_usb_jtag: capabilities descriptor set to 0x2000
Debug: 38 2 command.c:146 script_debug(): command - adapter speed 40000
Debug: 40 2 core.c:1822 jtag_config_khz(): handle jtag khz
Debug: 41 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 42 2 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 43 2 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/target/esp32c3.cfg
Debug: 44 2 command.c:146 script_debug(): command - transport select jtag
Warn : 45 2 transport.c:286 jim_transport_select(): Transport "jtag" was already selected
Debug: 46 2 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/bitsbytes.tcl
Debug: 47 2 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/memory.tcl
Debug: 48 2 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/mmr_helpers.tcl
Debug: 49 2 configuration.c:97 find_file(): found /home/logix/.espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/share/openocd/scripts/target/esp_common.cfg
Debug: 50 2 command.c:146 script_debug(): command - add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock are optional
Debug: 52 2 command.c:1115 help_add_command(): added 'program_esp' help text
Debug: 53 2 command.c:146 script_debug(): command - add_usage_text program_esp <filename> [address] [verify] [reset] [exit] [compress] [restore_clock]
Debug: 55 2 command.c:1141 help_add_command(): added 'program_esp' usage text
Debug: 56 2 command.c:146 script_debug(): command - add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project
Debug: 58 2 command.c:1115 help_add_command(): added 'program_esp_bins' help text
Debug: 59 2 command.c:146 script_debug(): command - add_usage_text program_esp_bins <build_dir> flasher_args.json [verify] [reset] [exit] [compress] [restore_clock]
Debug: 61 2 command.c:1141 help_add_command(): added 'program_esp_bins' usage text
Debug: 62 2 command.c:146 script_debug(): command - add_help_text esp_get_mac Print MAC address of the chip. Use a `format` argument to return formatted MAC value
Debug: 64 2 command.c:1115 help_add_command(): added 'esp_get_mac' help text
Debug: 65 2 command.c:146 script_debug(): command - add_usage_text esp_get_mac [format]
Debug: 67 2 command.c:1141 help_add_command(): added 'esp_get_mac' usage text
Debug: 68 2 command.c:146 script_debug(): command - jtag newtap esp32c3 cpu -irlen 5 -expected-id 0x00005c25
Debug: 69 2 tcl.c:572 jim_newtap_cmd(): Creating New Tap, Chip: esp32c3, Tap: cpu, Dotted: esp32c3.cpu, 4 params
Debug: 70 2 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen
Debug: 71 2 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id
Debug: 72 2 core.c:1488 jtag_tap_init(): Created Tap: esp32c3.cpu @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 73 2 command.c:146 script_debug(): command - target create esp32c3 esp32c3 -chain-position esp32c3.cpu -rtos FreeRTOS
Debug: 74 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 75 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 76 2 FreeRTOS.c:1242 FreeRTOS_create(): FreeRTOS_create
Debug: 77 2 command.c:376 register_command(): command 'set_enable_virtual' is already registered in 'riscv' context
Debug: 78 2 command.c:376 register_command(): command 'set_enable_virtual' is already registered in 'riscv' context
Debug: 79 2 command.c:146 script_debug(): command - esp32c3 configure -event reset-assert-post  esp32c3_soc_reset 
Debug: 80 2 command.c:146 script_debug(): command - esp32c3 configure -event halted 
    esp32c3_wdt_disable

Debug: 81 2 command.c:146 script_debug(): command - esp32c3 configure -event examine-end 
    # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
    arm semihosting enable
    arm semihosting_resexit enable

Debug: 82 2 command.c:146 script_debug(): command - esp32c3 configure -event gdb-attach 
    # 'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map
    halt
    if { [esp32c3_memprot_is_enabled] } {
        # 'reset halt' to disable memory protection and allow flasher to work correctly
        echo "Memory protection is enabled. Reset target to disable it..."
        reset halt
    }
    # by default mask interrupts while stepping
    riscv maskisr steponly

Debug: 83 2 command.c:146 script_debug(): command - esp32c3 configure -work-area-phys 0x40380000 -work-area-virt 0x40380000 -work-area-size 0x4000 -work-area-backup 1
Debug: 84 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 85 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 86 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 87 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 88 2 command.c:146 script_debug(): command - esp32c3 configure -alt-work-area-phys 0x3FC84000 -alt-work-area-virt 0x3FC84000 -alt-work-area-size 0x20000 -alt-work-area-backup 1
Debug: 89 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 90 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 91 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 92 2 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas
Debug: 93 2 command.c:146 script_debug(): command - flash bank esp32c3.flash esp32c3 0x0 0 0 0 esp32c3
Debug: 95 2 command.c:376 register_command(): command 'esp' is already registered in '<global>' context
Debug: 96 2 tcl.c:1319 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 97 2 command.c:146 script_debug(): command - flash bank esp32c3.irom esp32c3 0x0 0 0 0 esp32c3
Debug: 99 2 command.c:376 register_command(): command 'esp' is already registered in '<global>' context
Debug: 100 2 command.c:376 register_command(): command 'appimage_offset' is already registered in 'esp' context
Debug: 101 2 command.c:376 register_command(): command 'compression' is already registered in 'esp' context
Debug: 102 2 command.c:376 register_command(): command 'verify_bank_hash' is already registered in 'esp' context
Debug: 103 2 command.c:376 register_command(): command 'flash_stub_clock_boost' is already registered in 'esp' context
Debug: 104 2 tcl.c:1319 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 105 2 command.c:146 script_debug(): command - flash bank esp32c3.drom esp32c3 0x0 0 0 0 esp32c3
Debug: 107 2 command.c:376 register_command(): command 'esp' is already registered in '<global>' context
Debug: 108 2 command.c:376 register_command(): command 'appimage_offset' is already registered in 'esp' context
Debug: 109 2 command.c:376 register_command(): command 'compression' is already registered in 'esp' context
Debug: 110 2 command.c:376 register_command(): command 'verify_bank_hash' is already registered in 'esp' context
Debug: 111 2 command.c:376 register_command(): command 'flash_stub_clock_boost' is already registered in 'esp' context
Debug: 112 2 tcl.c:1319 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 113 2 command.c:146 script_debug(): command - riscv set_reset_timeout_sec 2
Debug: 115 2 command.c:146 script_debug(): command - riscv set_command_timeout_sec 5
Debug: 117 2 command.c:146 script_debug(): command - riscv set_prefer_sba on
Info : 119 2 server.c:312 add_service(): Listening on port 6666 for tcl connections
Info : 120 2 server.c:312 add_service(): Listening on port 4444 for telnet connections
Debug: 121 2 command.c:146 script_debug(): command - init
Debug: 123 2 command.c:146 script_debug(): command - target init
Debug: 125 2 command.c:146 script_debug(): command - target names
Debug: 126 2 command.c:146 script_debug(): command - esp32c3 cget -event gdb-flash-erase-start
Debug: 127 2 command.c:146 script_debug(): command - esp32c3 configure -event gdb-flash-erase-start reset init
Debug: 128 2 command.c:146 script_debug(): command - esp32c3 cget -event gdb-flash-write-end
Debug: 129 2 command.c:146 script_debug(): command - esp32c3 configure -event gdb-flash-write-end reset halt
Debug: 130 2 command.c:146 script_debug(): command - esp32c3 cget -event gdb-attach
Debug: 131 2 target.c:1661 handle_target_init_command(): Initializing targets...
Debug: 132 2 esp32c3.c:125 esp32c3_init_target(): enter
Debug: 133 37 semihosting_common.c:100 semihosting_common_init():  
Debug: 134 858 libusb_helper.c:334 jtag_libusb_choose_interface(): usb ep out 02
Debug: 135 858 libusb_helper.c:334 jtag_libusb_choose_interface(): usb ep in 83
Debug: 136 859 libusb_helper.c:342 jtag_libusb_choose_interface(): Claiming interface 2
Info : 137 861 esp_usb_jtag.c:730 esp_usb_jtag_init(): esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255
Debug: 138 864 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 139 864 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 140 864 esp_usb_jtag.c:789 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1
Debug: 141 864 esp_usb_jtag.c:805 esp_usb_jtag_speed(): esp_usb_jtag: setting divisor 1
Debug: 142 866 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 143 866 core.c:1789 adapter_khz_to_speed(): have interface set up
Debug: 144 866 esp_usb_jtag.c:789 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1
Info : 145 866 core.c:1565 adapter_init(): clock speed 40000 kHz
Debug: 146 866 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 147 866 command.c:146 script_debug(): command - transport init
Debug: 150 866 transport.c:229 handle_transport_init(): handle_transport_init
Debug: 151 868 core.c:718 legacy_jtag_add_reset(): SRST line released
Debug: 152 869 core.c:742 legacy_jtag_add_reset(): TRST line released
Debug: 153 869 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 154 870 command.c:146 script_debug(): command - jtag arp_init
Debug: 155 870 core.c:1578 jtag_init_inner(): Init JTAG chain
Debug: 156 870 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 157 872 core.c:1243 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 158 872 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 159 881 core.c:1142 jtag_examine_chain_display(): JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)
Debug: 160 882 core.c:1374 jtag_validate_ircapture(): IR capture validation scan
Debug: 161 885 core.c:1432 jtag_validate_ircapture(): esp32c3.cpu: IR capture 0x05
Debug: 162 885 command.c:146 script_debug(): command - dap init
Debug: 164 885 arm_dap.c:106 dap_init_all(): Initializing all DAPs ...
Debug: 165 885 openocd.c:160 handle_init_command(): Examining targets...
Debug: 166 885 target.c:1849 target_call_event_callbacks(): target event 19 (examine-start) for core esp32c3
Debug: 167 885 esp32c3.c:113 esp32c3_handle_target_event(): 19
Debug: 168 885 esp_riscv.c:185 esp_riscv_handle_target_event(): 19
Debug: 169 885 riscv.c:976 riscv_examine(): riscv_examine()
Debug: 170 889 riscv.c:404 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 171 889 riscv.c:986 riscv_examine(): dtmcontrol=0x1071
Debug: 172 889 riscv.c:988 riscv_examine():   version=0x1
Debug: 173 889 riscv-013.c:2031 init_target(): init
Debug: 174 893 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 175 893 riscv-013.c:1585 examine(): dtmcontrol=0x1071
Debug: 176 893 riscv-013.c:1586 examine():   dmireset=0
Debug: 177 893 riscv-013.c:1587 examine():   idle=1
Debug: 178 893 riscv-013.c:1588 examine():   dmistat=0
Debug: 179 893 riscv-013.c:1589 examine():   abits=7
Debug: 180 893 riscv-013.c:1590 examine():   version=1
Debug: 181 893 riscv-013.c:260 get_dm(): [0] Allocating new DM
Debug: 182 925 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 183 929 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 184 939 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 185 943 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 186 947 riscv-013.c:1635 examine(): dmstatus:  0x000fcca2
Debug: 187 947 riscv-013.c:1651 examine(): hartsellen=20
Debug: 188 954 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 189 958 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 190 970 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=4, ac_busy_delay=0
Debug: 191 974 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 192 986 riscv-013.c:1682 examine(): datacount=2 progbufsize=16
Debug: 193 1041 riscv-013.c:1720 examine(): Detected 1 harts.
Info : 194 1063 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 195 1071 riscv-013.c:3817 select_prepped_harts(): index=0, coreid=0, prepped=0
Debug: 196 1071 riscv-013.c:3858 riscv013_halt_go(): halting hart 0
Debug: 197 1103 riscv-013.c:802 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 198 1114 riscv-013.c:818 execute_abstract_command(): command 0x321008 failed; abstractcs=0x10000202
Debug: 199 1121 riscv-013.c:802 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 200 1140 riscv-013.c:1510 register_read_direct(): {0} misa = 0x40101104
Debug: 201 1140 riscv.c:3819 riscv_init_registers(): create register cache for 4194 registers
Debug: 202 1140 riscv-013.c:1778 examine():  hart 0: XLEN=32, misa=0x40101104
Debug: 203 1140 riscv-013.c:4445 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Info : 204 1171 riscv-013.c:1802 examine(): Examined RISC-V core; found 1 harts
Info : 205 1171 riscv-013.c:1806 examine():  hart 0: XLEN=32, misa=0x40101104
Debug: 206 1171 target.c:1849 target_call_event_callbacks(): target event 21 (examine-end) for core esp32c3
Debug: 207 1171 target.c:4849 target_handle_event(): target(0): esp32c3 (esp32c3) event: 21 (examine-end) action: 
    # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
    arm semihosting enable
    arm semihosting_resexit enable

Debug: 208 1171 command.c:146 script_debug(): command - arm semihosting enable
Debug: 209 1179 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0x30ca2
Debug: 210 1179 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 211 1194 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 212 1202 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 213 1202 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 214 1233 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 215 1248 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 216 1254 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 217 1269 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 218 1274 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 219 1286 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 220 1293 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 221 1309 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 222 1317 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 223 1331 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 224 1339 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 225 1354 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 226 1361 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 227 1361 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 228 1361 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 229 1378 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 230 1378 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 231 1378 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 232 1378 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 233 1385 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 234 1397 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 235 1420 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 236 1427 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 237 1435 riscv.c:2039 riscv_poll_hart():   triggered running
Debug: 239 1435 riscv_semihosting.c:188 riscv_semihosting_setup(): [esp32c3] enable=1
Debug: 240 1435 command.c:146 script_debug(): command - arm semihosting_resexit enable
Debug: 242 1443 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0x30ca2
Debug: 243 1443 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 244 1458 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 245 1466 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 246 1466 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 247 1497 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 248 1512 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 249 1519 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 250 1533 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 251 1541 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 252 1557 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 253 1565 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 254 1580 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 255 1587 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 256 1602 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 257 1609 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 258 1625 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 259 1633 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 260 1633 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 261 1633 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 262 1650 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 263 1650 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 264 1650 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 265 1650 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 266 1658 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 267 1669 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 268 1692 esp32c3.c:327 esp32c3_poll(): resumed core
Debug: 270 1700 esp32c3.c:113 esp32c3_handle_target_event(): 21
Debug: 271 1700 esp_riscv.c:185 esp_riscv_handle_target_event(): 21
Debug: 272 1700 command.c:146 script_debug(): command - flash init
Debug: 274 1708 tcl.c:1385 handle_flash_init_command(): Initializing flash devices...
Debug: 275 1708 command.c:146 script_debug(): command - nand init
Debug: 277 1716 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 278 1716 command.c:146 script_debug(): command - pld init
Debug: 280 1723 pld.c:206 handle_pld_init_command(): Initializing PLDs...
Info : 281 1723 gdb_server.c:3512 gdb_target_start(): starting gdb server for esp32c3 on 3333
Info : 282 1723 server.c:312 add_service(): Listening on port 3333 for gdb connections
Info : 283 1831 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 284 1949 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 285 1949 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 286 1965 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 287 1973 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 288 1973 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 289 2002 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 290 2018 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 291 2026 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 292 2041 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 293 2049 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 294 2064 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 295 2072 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 296 2087 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 297 2095 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 298 2110 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 299 2118 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 300 2133 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 301 2140 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 302 2140 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 303 2140 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 304 2160 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 305 2160 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 306 2160 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 307 2160 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 308 2168 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 309 2179 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 310 2202 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 311 2210 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 312 2325 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 313 2325 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 314 2341 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 315 2349 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 316 2349 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 317 2379 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 318 2395 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 319 2402 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 320 2416 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 321 2424 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 322 2438 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 323 2446 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 324 2462 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 325 2469 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 326 2485 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 327 2492 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 328 2508 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 329 2516 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 330 2516 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 331 2516 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 332 2536 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 333 2536 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 334 2536 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 335 2536 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 336 2544 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 337 2555 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 338 2579 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 339 2586 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 340 2701 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 341 2701 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 342 2716 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 343 2724 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 344 2724 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 345 2754 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 346 2770 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 347 2778 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 348 2793 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 349 2800 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 350 2816 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 351 2823 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 352 2839 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 353 2847 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 354 2861 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 355 2869 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 356 2885 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 357 2893 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 358 2893 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 359 2893 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 360 2913 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 361 2913 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 362 2913 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 363 2913 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 364 2920 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 365 2932 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 366 2956 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 367 2964 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 368 3079 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0x30ca2
Debug: 369 3079 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 370 3093 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 371 3100 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 372 3100 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 373 3132 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 374 3147 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 375 3154 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 376 3170 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 377 3178 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 378 3193 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 379 3200 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 380 3215 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 381 3223 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 382 3239 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 383 3247 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 384 3262 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 385 3270 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 386 3270 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 387 3270 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 388 3288 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 389 3288 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 390 3288 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 391 3288 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 392 3296 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 393 3308 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 394 3332 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 395 3339 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 396 3454 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 397 3454 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 398 3469 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 399 3477 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 400 3477 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 401 3508 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 402 3522 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 403 3529 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 404 3543 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 405 3551 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 406 3566 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 407 3574 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 408 3589 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 409 3597 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 410 3611 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 411 3617 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 412 3633 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 413 3640 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 414 3640 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 415 3640 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 416 3659 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 417 3659 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 418 3659 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 419 3659 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 420 3664 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 421 3676 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 422 3697 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 423 3706 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 424 3821 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 425 3821 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 426 3837 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 427 3845 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 428 3845 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 429 3876 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 430 3892 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 431 3900 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 432 3916 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 433 3924 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 434 3939 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 435 3947 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 436 3962 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 437 3969 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 438 3984 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 439 3992 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 440 4007 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 441 4015 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 442 4015 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 443 4015 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 444 4035 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 445 4035 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 446 4035 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 447 4035 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 448 4043 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 449 4054 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 450 4077 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 451 4085 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 452 4201 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 453 4202 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 454 4216 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 455 4223 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 456 4223 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 457 4253 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 458 4269 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 459 4276 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 460 4291 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 461 4299 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 462 4314 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 463 4322 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 464 4338 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 465 4346 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 466 4360 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 467 4367 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 468 4383 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 469 4391 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 470 4391 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 471 4391 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 472 4410 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 473 4410 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 474 4410 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 475 4410 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 476 4417 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 477 4429 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 478 4452 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 479 4459 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 480 4575 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 481 4575 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 482 4591 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 483 4599 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 484 4599 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 485 4630 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 486 4646 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 487 4654 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 488 4670 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 489 4678 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 490 4693 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 491 4700 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 492 4715 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 493 4723 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 494 4737 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 495 4744 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 496 4760 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 497 4768 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 498 4768 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 499 4768 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 500 4788 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 501 4788 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 502 4788 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 503 4788 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 504 4795 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 505 4806 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 506 4829 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 507 4837 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 508 4953 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0x30ca2
Debug: 509 4953 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 510 4969 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 511 4977 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 512 4977 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 513 5008 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 514 5022 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 515 5030 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 516 5045 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 517 5052 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 518 5068 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 519 5076 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 520 5090 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 521 5098 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 522 5113 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 523 5121 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 524 5136 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 525 5144 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 526 5144 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 527 5144 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 528 5164 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 529 5164 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 530 5164 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 531 5164 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 532 5171 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 533 5183 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 534 5205 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 535 5212 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 536 5327 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 537 5327 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 538 5344 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 539 5349 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 540 5349 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 541 5380 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 542 5395 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 543 5402 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 544 5418 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 545 5425 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 546 5441 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 547 5449 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 548 5463 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 549 5471 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 550 5487 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 551 5494 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 552 5507 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 553 5515 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 554 5515 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 555 5515 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 556 5534 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 557 5534 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 558 5534 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 559 5534 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 560 5542 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 561 5554 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 562 5576 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 563 5584 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 564 5699 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 565 5700 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 566 5715 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 567 5722 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 568 5722 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 569 5754 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 570 5770 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 571 5778 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 572 5793 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 573 5800 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 574 5816 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 575 5823 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 576 5839 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 577 5847 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 578 5862 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 579 5869 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 580 5885 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 581 5893 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 582 5893 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 583 5893 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 584 5912 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 585 5912 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 586 5912 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 587 5912 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 588 5920 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 589 5931 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 590 5954 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 591 5960 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 592 6076 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 593 6076 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 594 6091 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 595 6098 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 596 6099 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 597 6129 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 598 6145 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 599 6152 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 600 6167 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 601 6175 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 602 6191 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 603 6199 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 604 6214 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 605 6222 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 606 6237 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 607 6245 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 608 6259 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 609 6267 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 610 6267 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 611 6267 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 612 6287 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 613 6287 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 614 6287 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 615 6287 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 616 6295 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 617 6305 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 618 6328 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 619 6336 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 620 6452 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 621 6452 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 622 6466 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 623 6473 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 624 6473 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 625 6504 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 626 6520 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 627 6528 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 628 6543 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 629 6551 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 630 6566 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 631 6574 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 632 6589 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 633 6597 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 634 6612 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 635 6620 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 636 6633 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 637 6641 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 638 6641 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 639 6641 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 640 6660 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 641 6660 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 642 6660 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 643 6660 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 644 6668 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 645 6679 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 646 6702 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 647 6710 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 648 6827 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0x30ca2
Debug: 649 6828 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 650 6842 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 651 6850 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 652 6850 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 653 6881 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 654 6897 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 655 6905 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 656 6920 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 657 6928 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 658 6943 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 659 6950 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 660 6966 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 661 6974 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 662 6990 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 663 6998 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 664 7013 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 665 7020 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 666 7020 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 667 7020 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 668 7039 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 669 7039 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 670 7039 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 671 7039 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 672 7046 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 673 7057 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 674 7079 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 675 7087 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 676 7203 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0xf0ca2
Debug: 677 7204 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 678 7217 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 679 7225 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 680 7226 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 681 7257 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 682 7272 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 683 7279 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 684 7295 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 685 7303 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 686 7319 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 687 7327 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 688 7343 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 689 7351 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 690 7367 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 691 7375 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 692 7391 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 693 7399 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 694 7399 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 695 7399 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 696 7419 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 697 7419 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 698 7419 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 699 7419 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 700 7426 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 701 7435 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 702 7438 server.c:609 sig_handler(): Terminating on Signal 2
Debug: 703 7457 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 704 7466 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
Debug: 705 7472 command.c:146 script_debug(): command - shutdown
Debug: 706 7480 esp32c3.c:293 esp32c3_poll(): Core is out of reset: dmstatus 0x30ca2
Debug: 707 7480 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4   count:1 start address: 0x60004038
Debug: 708 7494 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x60004038
Debug: 709 7501 target.c:2654 target_read_u32(): address: 0x60004038, value: 0x0000000c
Debug: 710 7501 esp32c3.c:302 esp32c3_poll(): Halt core
Debug: 711 7532 target.c:2742 target_write_u32(): address: 0x6001f064, value: 0x50d83aa1
Debug: 712 7548 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 713 7555 target.c:2742 target_write_u32(): address: 0x6001f048, value: 0x00000000
Debug: 714 7569 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 715 7577 target.c:2742 target_write_u32(): address: 0x60020064, value: 0x50d83aa1
Debug: 716 7593 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 717 7599 target.c:2742 target_write_u32(): address: 0x60020048, value: 0x00000000
Debug: 718 7615 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 720 7623 target.c:2742 target_write_u32(): address: 0x600080a8, value: 0x50d83aa1
Debug: 721 7638 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 722 7646 target.c:2742 target_write_u32(): address: 0x60008090, value: 0x00000000
Debug: 723 7662 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 724 7669 FreeRTOS.c:1157 FreeRTOS_post_reset_cleanup(): FreeRTOS_post_reset_cleanup
Debug: 725 7669 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0
Debug: 726 7669 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 727 7689 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0xc3
Debug: 728 7689 esp32c3.c:266 esp32c3_core_ebreaks_enable(): DCSR: c3
Debug: 729 7689 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xb0c3 to register dcsr on hart 0
Debug: 730 7689 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0xb0c3
Debug: 731 7697 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 732 7709 esp32c3.c:323 esp32c3_poll(): Resume core
Debug: 733 7733 esp32c3.c:327 esp32c3_poll(): resumed core
Info : 734 7741 riscv-013.c:3950 riscv013_is_halted(): Hart 0 unexpectedly reset
User : 736 7749 server.c:755 handle_shutdown_command(): shutdown command invoked
Debug: 737 7749 riscv.c:483 riscv_deinit_target(): riscv_deinit_target()
Debug: 738 7749 riscv-013.c:1543 deinit_target(): riscv_deinit_target()
Debug: 739 7750 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas



### Expected behavior

I expect openocd to start and connect to the device.

### Screenshots

_No response_
igrr commented 2 years ago

Hi @andrew-elder, this part of the log looks okay from OpenOCD perspective:

Info : Hart 0 unexpectedly reset
Info : Hart 0 unexpectedly reset
Info : Hart 0 unexpectedly reset
Info : Hart 0 unexpectedly reset

Usually this means that the CPU was reset — either by the program itself (esp_restart call) or by one of the watchdogs. You can check what is happening with the program by observing serial output. The serial port will be visible when you connect a USB cable to the built-in USB peripheral of the ESP32-C3.

andrew-elder commented 2 years ago

Hi @igrr, Well you are correct. Thanks for the prompt response. See below

ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
Saved PC:0x403d1546
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd6100,len:0x16b4
load:0x403ce000,len:0x930
load:0x403d0000,len:0x2d40
entry 0x403ce000
I (35) boot: ESP-IDF v4.4 2nd stage bootloader
I (35) boot: compile time 08:47:20
I (35) boot: chip revision: 3
I (36) boot.esp32c3: SPI Speed      : 80MHz
I (41) boot.esp32c3: SPI Mode       : DIO
I (46) boot.esp32c3: SPI Flash Size : 2MB
I (51) boot: Enabling RNG early entropy source...
I (56) boot: Partition Table:
I (60) boot: ## Label            Usage          Type ST Offset   Length
I (67) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (74) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (82) boot:  2 factory          factory app      00 00 00010000 0013d620
I (89) boot: End of partition table
E (94) esp_image: image at 0x10000 has invalid magic byte (nothing flashed here?)
E (102) boot: Factory app partition is not bootable
E (107) boot: No bootable app partitions in the partition table
ESP-ROM:esp32c3-api1-20210207
...

It seems like openocd JTAG does not support recovery from this really bad state (which I don't know how I got on to). My only path forward is reflashing using serial? I don't have easy access to the fully functional serial port because I've moved a couple of resistors to bypass the CP210.

andrew-elder commented 2 years ago

@igrr - if I was using JTAG with a JLink adapter, would I have this issue?

igrr commented 2 years ago

@andrew-elder When you connect ESP32-C3 over the built-in USB, you get JTAG and serial (it's a composite device). So you should be able to reflash via USB CDC — just point esptool to the port which appears in your system. It is not necessary to return to CP2102 for this.

That said, what do you mean by "JTAG does not support recovery from this really bad state"? It looks like you don't have an application flashed yet. Are you trying to flash the application with OpenOCD and is that failing somehow?

Normally if you'd like to run your program on the ESP32-C3, you need to:

1) build the program first, usually using idf.py build 2) when the program is built, flash it to the device. You can do this either with:

andrew-elder commented 2 years ago

@igrr - here is the result of trying to flash using idf.py

logix@ubuntu:~/sw/krado/ledc$ idf.py -p /dev/ttyACM0 flash
Executing action: flash
Running ninja in directory /home/logix/sw/krado/ledc/build
Executing "ninja flash"...
[1/5] cd /home/logix/sw/krado/ledc/build/esp-idf/esptool_py && /home/logix/.espressif/python_env/idf4.4_py3..../home/logix/sw/krado/ledc/build/partition_table/partition-table.bin /home/logix/sw/krado/ledc/build/ledc.bin
ledc.bin binary size 0x271f0 bytes. Smallest app partition is 0x100000 bytes. 0xd8e10 bytes (85%) free.
[2/5] Performing build step for 'bootloader'
[1/1] cd /home/logix/sw/krado/ledc/build/bootloader/esp-idf/esptool_py && /home/logix/.espressif/python_env/idf4.4_py3.8_env/bin/python /home/logix/esp/esp-idf/components/partition_table/check_sizes.py --offset 0x8000 bootloader 0x0 /home/logix/sw/krado/ledc/build/bootloader/bootloader.bin
Bootloader binary size 0x4d80 bytes. 0x3280 bytes (39%) free.
[2/3] cd /home/logix/esp/esp-idf/components/esptool_py && /usr/bin/cmake -D IDF_PATH="/home/logix/esp/esp-id...ORY="/home/logix/sw/krado/ledc/build" -P /home/logix/esp/esp-idf/components/esptool_py/run_serial_tool.cmake
esptool.py esp32c3 -p /dev/ttyACM0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 ledc.bin 0x8000 partition_table/partition-table.bin
esptool.py v3.2-dev
Serial port /dev/ttyACM0
Connecting....
Chip is ESP32-C3 (revision 3)
Features: Wi-Fi
Crystal is 40MHz
MAC: 84:f7:03:06:f2:2c
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 460800
Changed.
Configuring flash size...
Flash will be erased from 0x00000000 to 0x00004fff...
Flash will be erased from 0x00010000 to 0x00037fff...
Flash will be erased from 0x00008000 to 0x00008fff...
Compressed 19840 bytes to 12002...
Writing at 0x00000000... (100 %)
Wrote 19840 bytes (12002 compressed) at 0x00000000 in 0.4 seconds (effective 384.4 kbit/s)...

A fatal error occurred: Packet content transfer stopped (received 25 bytes)
CMake Error at run_serial_tool.cmake:56 (message):
  /home/logix/.espressif/python_env/idf4.4_py3.8_env/bin/python
  /home/logix/esp/esp-idf/components/esptool_py/esptool/esptool.py --chip
  esp32c3 failed

FAILED: CMakeFiles/flash 
cd /home/logix/esp/esp-idf/components/esptool_py && /usr/bin/cmake -D IDF_PATH="/home/logix/esp/esp-idf" -D SERIAL_TOOL="/home/logix/.espressif/python_env/idf4.4_py3.8_env/bin/python /home/logix/esp/esp-idf/components/esptool_py/esptool/esptool.py --chip esp32c3" -D SERIAL_TOOL_ARGS="--before=default_reset --after=hard_reset write_flash @flash_args" -D WORKING_DIRECTORY="/home/logix/sw/krado/ledc/build" -P /home/logix/esp/esp-idf/components/esptool_py/run_serial_tool.cmake
ninja: build stopped: subcommand failed.
ninja failed with exit code 1

And this is what idf.py monitor shows

ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
Saved PC:0x403d1546
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd6100,len:0x16b4
load:0x403ce000,len:0x930
load:0x403d0000,len:0x2d40
entry 0x403ce000
I (24) boot: ESP-IDF v4.4 2nd stage bootloader
I (24) boot: compile time 07:54:07
I (24) boot: chip revision: 3
I (25) boot.esp32c3: SPI Speed      : 80MHz
I (30) boot.esp32c3: SPI Mode       : DIO
I (35) boot.esp32c3: SPI Flash Size : 2MB
I (39) boot: Enabling RNG early entropy source...
I (45) boot: Partition Table:
I (48) boot: ## Label            Usage          Type ST Offset   Length
I (56) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (63) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (71) boot:  2 factory          factory app      00 00 00010000 0013d620
I (78) boot: End of partition table
E (82) esp_image: image at 0x10000 has invalid magic byte (nothing flashed here?)
E (90) boot: Factory app partition is not bootable
E (96) boot: No bootable app partitions in the partition table
ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
Saved PC:0x403d1546
...

I'm building examples/ledc. It seems like the flashing operation is not completing correctly?

I have never successfully flashed an application to the DevKit. It was running the default Rainmaker image that it shipped with from the factory. If it is no long running bootable code, it is because all my attempts to flash an application across JTAG have resulted in a non-bootable/corrupt state.

igrr commented 2 years ago

@andrew-elder Thanks for the details, that's really interesting! Do you have a chance to try some combination of: different USB cable, different USB port (e.g. internal/external), maybe different OS (if you have another computer)? We did get some reports of ESP32-C3 built-in USB peripheral not working well with certain USB hubs or cables, but didn't find enough information to narrow down the issue.

(cc @radim.karnis for esptool flashing issue)

andrew-elder commented 2 years ago

@iggr - ok, so I tried a different cable - no joy. I tried a completely different machine and had success.

logix@andrew-ub1:~/projects/krado/sw/ledc/ledc_basic$ idf.py -p /dev/ttyACM0 flash
Executing action: flash
Running ninja in directory /home/logix/projects/krado/sw/ledc/ledc_basic/build
Executing "ninja flash"...
[1/5] cd /home/logix/projects/krado/sw/ledc/ledc_basic/build/esp-idf/esptool_py ...partition-table.bin /home/logix/projects/krado/sw/ledc/ledc_basic/build/ledc.bin
ledc.bin binary size 0x261d0 bytes. Smallest app partition is 0x100000 bytes. 0xd9e30 bytes (85%) free.
[2/5] Performing build step for 'bootloader'
[1/1] cd /home/logix/projects/krado/sw/ledc/ledc_basic/build/bootloader/esp-idf/esptool_py && /home/logix/.espressif/python_env/idf4.4_py3.8_env/bin/python /home/logix/esp/esp-idf/components/partition_table/check_sizes.py --offset 0x8000 bootloader 0x0 /home/logix/projects/krado/sw/ledc/ledc_basic/build/bootloader/bootloader.bin
Bootloader binary size 0x4d80 bytes. 0x3280 bytes (39%) free.
[2/3] cd /home/logix/esp/esp-idf/components/esptool_py && /usr/bin/cmake -D IDF_...ic/build" -P /home/logix/esp/esp-idf/components/esptool_py/run_serial_tool.cmake
esptool.py esp32c3 -p /dev/ttyACM0 -b 460800 --before=default_reset --after=hard_reset write_flash --flash_mode dio --flash_freq 80m --flash_size 2MB 0x0 bootloader/bootloader.bin 0x10000 ledc.bin 0x8000 partition_table/partition-table.bin
esptool.py v3.2-dev
Serial port /dev/ttyACM0
Connecting....
Chip is ESP32-C3 (revision 3)
Features: Wi-Fi
Crystal is 40MHz
MAC: 84:f7:03:06:f2:2c
Uploading stub...
Running stub...
Stub running...
Changing baud rate to 460800
Changed.
Configuring flash size...
Flash will be erased from 0x00000000 to 0x00004fff...
Flash will be erased from 0x00010000 to 0x00036fff...
Flash will be erased from 0x00008000 to 0x00008fff...
Compressed 19840 bytes to 12000...
Writing at 0x00000000... (100 %)
Wrote 19840 bytes (12000 compressed) at 0x00000000 in 0.4 seconds (effective 408.0 kbit/s)...
Hash of data verified.
Compressed 156112 bytes to 83113...
Writing at 0x00010000... (16 %)
Writing at 0x00019ce0... (33 %)
Writing at 0x00020689... (50 %)
Writing at 0x00027d49... (66 %)
Writing at 0x0002e55b... (83 %)
Writing at 0x000358ea... (100 %)
Wrote 156112 bytes (83113 compressed) at 0x00010000 in 2.3 seconds (effective 538.2 kbit/s)...
Hash of data verified.
Compressed 3072 bytes to 103...
Writing at 0x00008000... (100 %)
Wrote 3072 bytes (103 compressed) at 0x00008000 in 0.1 seconds (effective 451.3 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting via RTS pin...
Done

My other (failing) setup used a Lenovo X1 Extreme laptop running Windows 10. The esp-idf setup was running on a Linux Ubuntu 20.04 installation on VMware. I tried both a USB laptop port and another port in the Thinkpad dock and neither of them worked.

Note: I haven't yet tried the debugging step, but I'm sure it will work. This is much further than I got before.

andrew-elder commented 2 years ago

I set up the ESP32C3 tools on the same Lenovo laptop mentioned above using the "host" Windows OS, and I successfully flashed across USB openocd port. I would have to conclude there is an issue running openocd in a Linux VM. I'm using VMware Workstation 15.5.7 for future reference.