Wouldn't allow me to do the whole debug log so including the tail here

Debug: 1940 10343 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 1941 10350 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 1942 10359 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 1943 10366 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 1944 10375 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 1945 10380 target.c:2466 target_write_buffer(): writing buffer of 268 byte at 0x40381c00 Debug: 1946 10387 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 1947 10394 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 1948 10401 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 1949 10409 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 1950 10414 esp_algorithm.c:320 algorithm_load_func_image(): addr 0x00000000, sz 769, flags 0 Debug: 1951 10419 esp_algorithm.c:352 algorithm_load_func_image(): DATA sec size 769 -> 772 Debug: 1952 10424 esp_algorithm.c:357 algorithm_load_func_image(): BSS sec size 289 -> 292 Debug: 1953 10429 target.c:2116 alloc_working_area_try_do(): allocated new working area of 1064 bytes at address 0x3fc84000 Debug: 1954 10437 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fc84427 (1064 bytes) Debug: 1955 10440 target.c:1983 print_wa_layout(): 0x3fc84428-0x3fca3fff (130008 bytes) Debug: 1956 10445 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000 Debug: 1957 10452 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 1958 10459 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 1959 10468 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 1960 10476 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 1961 10485 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 1962 10490 target.c:2466 target_write_buffer(): writing buffer of 257 byte at 0x3fc84200 Debug: 1963 10498 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 1964 10506 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84280 Debug: 1965 10515 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 1966 10521 riscv-013.c:2908 mem_should_skip_sysbus(): Skipping mem write via system bus - unsupported size. Debug: 1967 10529 riscv-013.c:3815 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc84300 Debug: 1968 10534 riscv-013.c:800 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1969 10541 riscv-013.c:1504 register_read_direct(): {0} s0 = 0x0 Debug: 1970 10547 riscv-013.c:800 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 1971 10557 riscv-013.c:1504 register_read_direct(): {0} s1 = 0x0 Debug: 1972 10561 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x00940023) Debug: 1973 10567 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x00140413) Debug: 1974 10572 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1975 10577 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1976 10581 riscv-013.c:3872 write_memory_progbuf(): writing until final address 0x000000003fc84301 Debug: 1977 10585 riscv-013.c:3875 write_memory_progbuf(): transferring burst starting at address 0x000000003fc84300 Debug: 1978 10590 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x3fc84300 Debug: 1979 10596 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 1980 10604 riscv-013.c:800 execute_abstract_command(): command=0x271009; access register, size=32, postexec=1, transfer=1, write=1, regno=0x1009 Debug: 1981 10614 batch.c:91 riscv_batch_run(): Ignoring empty batch. Debug: 1982 10619 riscv-013.c:3955 write_memory_progbuf(): successful (partial?) memory write Debug: 1983 10625 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x0 Debug: 1984 10629 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 1985 10637 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0 Debug: 1986 10642 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 1987 10650 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 1988 10664 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 1989 10669 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1990 10673 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1991 10678 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 1992 10685 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via program buffer. Debug: 1993 10691 target.c:2116 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3fc84428 Debug: 1994 10696 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fc84427 (1064 bytes) Debug: 1995 10700 target.c:1983 print_wa_layout(): 0x3fc84428-0x3fc84827 (1024 bytes) Debug: 1996 10704 target.c:1983 print_wa_layout(): 0x3fc84828-0x3fca3fff (128984 bytes) Debug: 1997 10708 target.c:2116 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381d0c Debug: 1998 10716 target.c:1983 print_wa_layout(): 0x40380000-0x40381d0b (7436 bytes) Debug: 1999 10721 target.c:1983 print_wa_layout(): * 0x40381d0c-0x40381d0f (4 bytes) Debug: 2000 10725 target.c:1983 print_wa_layout(): 0x40381d10-0x40383fff (8944 bytes) Debug: 2001 10729 target.c:2466 target_write_buffer(): writing buffer of 4 byte at 0x40381d0c Debug: 2002 10735 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381d0c Debug: 2003 10742 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2004 10748 esp_algorithm.c:443 algorithm_load_func_image(): Stub loaded in 1031.61 ms Debug: 2005 10753 esp_riscv_algorithm.c:53 esp_riscv_algo_regs_init_start(): Check stack addr 0x3fc84828 Debug: 2006 10758 esp_riscv_algorithm.c:56 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc84820 Debug: 2007 10764 esp_riscv_algorithm.c:96 esp_riscv_algo_init(): Set arg[0] = 4 (a0) Debug: 2008 10769 esp_algorithm.c:198 algorithm_run(): Algorithm start @ 0x40381d0c, stack 1024 bytes @ 0x3fc84828 Debug: 2009 10774 esp_riscv.c:316 esp_riscv_start_algorithm(): save ra Debug: 2010 10778 riscv.c:3522 riscv_get_register(): [esp32c3] ra: 0 (cached) Debug: 2011 10781 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from ra (valid=1) Debug: 2012 10787 esp_riscv.c:316 esp_riscv_start_algorithm(): save sp Debug: 2013 10790 riscv.c:3522 riscv_get_register(): [esp32c3] sp: 0 (cached) Debug: 2014 10794 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from sp (valid=1) Debug: 2015 10799 esp_riscv.c:316 esp_riscv_start_algorithm(): save gp Debug: 2016 10802 riscv.c:3522 riscv_get_register(): [esp32c3] gp: 0 (cached) Debug: 2017 10805 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from gp (valid=1) Debug: 2018 10809 esp_riscv.c:316 esp_riscv_start_algorithm(): save tp Debug: 2019 10814 riscv.c:3522 riscv_get_register(): [esp32c3] tp: 0 (cached) Debug: 2020 10817 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tp (valid=1) Debug: 2021 10821 esp_riscv.c:316 esp_riscv_start_algorithm(): save t0 Debug: 2022 10824 riscv.c:3522 riscv_get_register(): [esp32c3] t0: 0 (cached) Debug: 2023 10827 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t0 (valid=1) Debug: 2024 10832 esp_riscv.c:316 esp_riscv_start_algorithm(): save t1 Debug: 2025 10835 riscv.c:3522 riscv_get_register(): [esp32c3] t1: 0 (cached) Debug: 2026 10839 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t1 (valid=1) Debug: 2027 10842 esp_riscv.c:316 esp_riscv_start_algorithm(): save t2 Debug: 2028 10847 riscv.c:3522 riscv_get_register(): [esp32c3] t2: 0 (cached) Debug: 2029 10851 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1) Debug: 2030 10854 esp_riscv.c:316 esp_riscv_start_algorithm(): save fp Debug: 2031 10857 riscv.c:3522 riscv_get_register(): [esp32c3] s0: 0 (cached) Debug: 2032 10862 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from fp (valid=1) Debug: 2033 10866 esp_riscv.c:316 esp_riscv_start_algorithm(): save s1 Debug: 2034 10869 riscv.c:3522 riscv_get_register(): [esp32c3] s1: 0 (cached) Debug: 2035 10872 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s1 (valid=1) Debug: 2036 10877 esp_riscv.c:316 esp_riscv_start_algorithm(): save a0 Debug: 2037 10880 riscv.c:3522 riscv_get_register(): [esp32c3] a0: 0 (cached) Debug: 2038 10885 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1) Debug: 2039 10890 esp_riscv.c:316 esp_riscv_start_algorithm(): save a1 Debug: 2040 10895 riscv.c:3522 riscv_get_register(): [esp32c3] a1: 0 (cached) Debug: 2041 10898 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a1 (valid=1) Debug: 2042 10902 esp_riscv.c:316 esp_riscv_start_algorithm(): save a2 Debug: 2043 10905 riscv.c:3522 riscv_get_register(): [esp32c3] a2: 0 (cached) Debug: 2044 10909 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a2 (valid=1) Debug: 2045 10914 esp_riscv.c:316 esp_riscv_start_algorithm(): save a3 Debug: 2046 10918 riscv.c:3522 riscv_get_register(): [esp32c3] a3: 0 (cached) Debug: 2047 10924 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a3 (valid=1) Debug: 2048 10929 esp_riscv.c:316 esp_riscv_start_algorithm(): save a4 Debug: 2049 10932 riscv.c:3522 riscv_get_register(): [esp32c3] a4: 0 (cached) Debug: 2050 10935 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a4 (valid=1) Debug: 2051 10940 esp_riscv.c:316 esp_riscv_start_algorithm(): save a5 Debug: 2052 10943 riscv.c:3522 riscv_get_register(): [esp32c3] a5: 0 (cached) Debug: 2053 10947 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a5 (valid=1) Debug: 2054 10951 esp_riscv.c:316 esp_riscv_start_algorithm(): save a6 Debug: 2055 10954 riscv.c:3522 riscv_get_register(): [esp32c3] a6: 0 (cached) Debug: 2056 10959 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1) Debug: 2057 10963 esp_riscv.c:316 esp_riscv_start_algorithm(): save a7 Debug: 2058 10966 riscv.c:3522 riscv_get_register(): [esp32c3] a7: 0 (cached) Debug: 2059 10969 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1) Debug: 2060 10975 esp_riscv.c:316 esp_riscv_start_algorithm(): save s2 Debug: 2061 10979 riscv.c:3522 riscv_get_register(): [esp32c3] s2: 0 (cached) Debug: 2062 10982 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s2 (valid=1) Debug: 2063 10986 esp_riscv.c:316 esp_riscv_start_algorithm(): save s3 Debug: 2064 10990 riscv.c:3522 riscv_get_register(): [esp32c3] s3: 0 (cached) Debug: 2065 10993 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1) Debug: 2066 10997 esp_riscv.c:316 esp_riscv_start_algorithm(): save s4 Debug: 2067 11000 riscv.c:3522 riscv_get_register(): [esp32c3] s4: 0 (cached) Debug: 2068 11005 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1) Debug: 2069 11009 esp_riscv.c:316 esp_riscv_start_algorithm(): save s5 Debug: 2070 11012 riscv.c:3522 riscv_get_register(): [esp32c3] s5: 0 (cached) Debug: 2071 11015 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1) Debug: 2072 11020 esp_riscv.c:316 esp_riscv_start_algorithm(): save s6 Debug: 2073 11023 riscv.c:3522 riscv_get_register(): [esp32c3] s6: 0 (cached) Debug: 2074 11027 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1) Debug: 2075 11033 esp_riscv.c:316 esp_riscv_start_algorithm(): save s7 Debug: 2076 11036 riscv.c:3522 riscv_get_register(): [esp32c3] s7: 0 (cached) Debug: 2077 11040 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1) Debug: 2078 11044 esp_riscv.c:316 esp_riscv_start_algorithm(): save s8 Debug: 2079 11049 riscv.c:3522 riscv_get_register(): [esp32c3] s8: 0 (cached) Debug: 2080 11052 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1) Debug: 2081 11056 esp_riscv.c:316 esp_riscv_start_algorithm(): save s9 Debug: 2082 11059 riscv.c:3522 riscv_get_register(): [esp32c3] s9: 0 (cached) Debug: 2083 11062 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1) Debug: 2084 11068 esp_riscv.c:316 esp_riscv_start_algorithm(): save s10 Debug: 2085 11071 riscv.c:3522 riscv_get_register(): [esp32c3] s10: 0 (cached) Debug: 2086 11074 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1) Debug: 2087 11078 esp_riscv.c:316 esp_riscv_start_algorithm(): save s11 Debug: 2088 11082 riscv.c:3522 riscv_get_register(): [esp32c3] s11: 0 (cached) Debug: 2089 11086 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1) Debug: 2090 11090 esp_riscv.c:316 esp_riscv_start_algorithm(): save t3 Debug: 2091 11093 riscv.c:3522 riscv_get_register(): [esp32c3] t3: 0 (cached) Debug: 2092 11097 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1) Debug: 2093 11101 esp_riscv.c:316 esp_riscv_start_algorithm(): save t4 Debug: 2094 11104 riscv.c:3522 riscv_get_register(): [esp32c3] t4: 0 (cached) Debug: 2095 11107 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1) Debug: 2096 11113 esp_riscv.c:316 esp_riscv_start_algorithm(): save t5 Debug: 2097 11116 riscv.c:3522 riscv_get_register(): [esp32c3] t5: 0 (cached) Debug: 2098 11119 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1) Debug: 2099 11123 esp_riscv.c:316 esp_riscv_start_algorithm(): save t6 Debug: 2100 11127 riscv.c:3522 riscv_get_register(): [esp32c3] t6: 0 (cached) Debug: 2101 11131 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1) Debug: 2102 11135 esp_riscv.c:316 esp_riscv_start_algorithm(): save pc Debug: 2103 11139 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc Debug: 2104 11145 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 2105 11153 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40000000 Debug: 2106 11159 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40000000 Debug: 2107 11164 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40000000 Debug: 2108 11169 riscv.c:3893 register_get(): [esp32c3] read 0x40000000 from pc (valid=0) Debug: 2109 11175 esp_riscv.c:316 esp_riscv_start_algorithm(): save mstatus Debug: 2110 11179 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mstatus Debug: 2111 11184 riscv-013.c:800 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 2112 11195 riscv-013.c:1504 register_read_direct(): {0} mstatus = 0x201800 Debug: 2113 11199 riscv.c:3539 riscv_get_register(): [esp32c3] mstatus: 201800 Debug: 2114 11203 riscv.c:3893 register_get(): [esp32c3] read 0x00201800 from mstatus (valid=1) Debug: 2115 11208 esp_riscv.c:316 esp_riscv_start_algorithm(): save misa Debug: 2116 11212 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register misa Debug: 2117 11216 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 2118 11226 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104 Debug: 2119 11230 riscv.c:3539 riscv_get_register(): [esp32c3] misa: 40101104 Debug: 2120 11234 riscv.c:3893 register_get(): [esp32c3] read 0x40101104 from misa (valid=1) Debug: 2121 11241 esp_riscv.c:316 esp_riscv_start_algorithm(): save mtvec Debug: 2122 11244 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr773 Debug: 2123 11249 riscv-013.c:800 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 2124 11257 riscv-013.c:1504 register_read_direct(): {0} csr773 = 0x1 Debug: 2125 11262 riscv.c:3539 riscv_get_register(): [esp32c3] csr773: 1 Debug: 2126 11266 riscv.c:3893 register_get(): [esp32c3] read 0x00000001 from mtvec (valid=0) Debug: 2127 11272 esp_riscv.c:316 esp_riscv_start_algorithm(): save mscratch Debug: 2128 11275 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr832 Debug: 2129 11279 riscv-013.c:800 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 2130 11290 riscv-013.c:1504 register_read_direct(): {0} csr832 = 0x0 Debug: 2131 11294 riscv.c:3539 riscv_get_register(): [esp32c3] csr832: 0 Debug: 2132 11297 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mscratch (valid=0) Debug: 2133 11302 esp_riscv.c:316 esp_riscv_start_algorithm(): save mepc Debug: 2134 11306 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mepc Debug: 2135 11310 riscv-013.c:800 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 2136 11320 riscv-013.c:1504 register_read_direct(): {0} mepc = 0x0 Debug: 2137 11323 riscv.c:3539 riscv_get_register(): [esp32c3] mepc: 0 Debug: 2138 11326 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mepc (valid=1) Debug: 2139 11330 esp_riscv.c:316 esp_riscv_start_algorithm(): save mcause Debug: 2140 11335 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mcause Debug: 2141 11339 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 2142 11348 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x0 Debug: 2143 11353 riscv.c:3539 riscv_get_register(): [esp32c3] mcause: 0 Debug: 2144 11357 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mcause (valid=1) Debug: 2145 11363 esp_riscv.c:316 esp_riscv_start_algorithm(): save mtval Debug: 2146 11366 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr835 Debug: 2147 11370 riscv-013.c:800 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 2148 11379 riscv-013.c:1504 register_read_direct(): {0} csr835 = 0x0 Debug: 2149 11383 riscv.c:3539 riscv_get_register(): [esp32c3] csr835: 0 Debug: 2150 11386 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mtval (valid=0) Debug: 2151 11390 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg0 Debug: 2152 11393 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr928 Debug: 2153 11398 riscv-013.c:800 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 2154 11406 riscv-013.c:1504 register_read_direct(): {0} csr928 = 0x0 Debug: 2155 11412 riscv.c:3539 riscv_get_register(): [esp32c3] csr928: 0 Debug: 2156 11416 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg0 (valid=0) Debug: 2157 11420 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg1 Debug: 2158 11423 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr929 Debug: 2159 11429 riscv-013.c:800 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 2160 11439 riscv-013.c:1504 register_read_direct(): {0} csr929 = 0x0 Debug: 2161 11443 riscv.c:3539 riscv_get_register(): [esp32c3] csr929: 0 Debug: 2162 11446 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg1 (valid=0) Debug: 2163 11450 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg2 Debug: 2164 11453 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr930 Debug: 2165 11458 riscv-013.c:800 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 2166 11468 riscv-013.c:1504 register_read_direct(): {0} csr930 = 0x0 Debug: 2167 11473 riscv.c:3539 riscv_get_register(): [esp32c3] csr930: 0 Debug: 2168 11477 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg2 (valid=0) Debug: 2169 11481 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg3 Debug: 2170 11484 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr931 Debug: 2171 11489 riscv-013.c:800 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 Debug: 2172 11499 riscv-013.c:1504 register_read_direct(): {0} csr931 = 0x0 Debug: 2173 11502 riscv.c:3539 riscv_get_register(): [esp32c3] csr931: 0 Debug: 2174 11507 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg3 (valid=0) Debug: 2175 11512 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr0 Debug: 2176 11516 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr944 Debug: 2177 11521 riscv-013.c:800 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 2178 11531 riscv-013.c:1504 register_read_direct(): {0} csr944 = 0x0 Debug: 2179 11537 riscv.c:3539 riscv_get_register(): [esp32c3] csr944: 0 Debug: 2180 11540 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr0 (valid=0) Debug: 2181 11544 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr1 Debug: 2182 11548 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr945 Debug: 2183 11553 riscv-013.c:800 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 2184 11561 riscv-013.c:1504 register_read_direct(): {0} csr945 = 0x0 Debug: 2185 11565 riscv.c:3539 riscv_get_register(): [esp32c3] csr945: 0 Debug: 2186 11569 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr1 (valid=0) Debug: 2187 11573 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr2 Debug: 2188 11577 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr946 Debug: 2189 11581 riscv-013.c:800 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 2190 11590 riscv-013.c:1504 register_read_direct(): {0} csr946 = 0x0 Debug: 2191 11594 riscv.c:3539 riscv_get_register(): [esp32c3] csr946: 0 Debug: 2192 11597 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr2 (valid=0) Debug: 2193 11602 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr3 Debug: 2194 11605 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr947 Debug: 2195 11609 riscv-013.c:800 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 2196 11618 riscv-013.c:1504 register_read_direct(): {0} csr947 = 0x0 Debug: 2197 11621 riscv.c:3539 riscv_get_register(): [esp32c3] csr947: 0 Debug: 2198 11625 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr3 (valid=0) Debug: 2199 11631 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr4 Debug: 2200 11635 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr948 Debug: 2201 11641 riscv-013.c:800 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 2202 11653 riscv-013.c:1504 register_read_direct(): {0} csr948 = 0x0 Debug: 2203 11657 riscv.c:3539 riscv_get_register(): [esp32c3] csr948: 0 Debug: 2204 11660 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr4 (valid=0) Debug: 2205 11665 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr5 Debug: 2206 11669 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr949 Debug: 2207 11673 riscv-013.c:800 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 2208 11684 riscv-013.c:1504 register_read_direct(): {0} csr949 = 0x0 Debug: 2209 11687 riscv.c:3539 riscv_get_register(): [esp32c3] csr949: 0 Debug: 2210 11690 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr5 (valid=0) Debug: 2211 11695 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr6 Debug: 2212 11698 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr950 Debug: 2213 11702 riscv-013.c:800 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 2214 11711 riscv-013.c:1504 register_read_direct(): {0} csr950 = 0x0 Debug: 2215 11714 riscv.c:3539 riscv_get_register(): [esp32c3] csr950: 0 Debug: 2216 11717 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr6 (valid=0) Debug: 2217 11722 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr7 Debug: 2218 11726 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr951 Debug: 2219 11731 riscv-013.c:800 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 2220 11744 riscv-013.c:1504 register_read_direct(): {0} csr951 = 0x0 Debug: 2221 11747 riscv.c:3539 riscv_get_register(): [esp32c3] csr951: 0 Debug: 2222 11750 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr7 (valid=0) Debug: 2223 11754 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr8 Debug: 2224 11759 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr952 Debug: 2225 11764 riscv-013.c:800 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 2226 11773 riscv-013.c:1504 register_read_direct(): {0} csr952 = 0x0 Debug: 2227 11777 riscv.c:3539 riscv_get_register(): [esp32c3] csr952: 0 Debug: 2228 11780 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr8 (valid=0) Debug: 2229 11784 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr9 Debug: 2230 11789 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr953 Debug: 2231 11792 riscv-013.c:800 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 2232 11801 riscv-013.c:1504 register_read_direct(): {0} csr953 = 0x0 Debug: 2233 11805 riscv.c:3539 riscv_get_register(): [esp32c3] csr953: 0 Debug: 2234 11808 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr9 (valid=0) Debug: 2235 11812 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr10 Debug: 2236 11815 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr954 Debug: 2237 11821 riscv-013.c:800 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 2238 11831 riscv-013.c:1504 register_read_direct(): {0} csr954 = 0x0 Debug: 2239 11835 riscv.c:3539 riscv_get_register(): [esp32c3] csr954: 0 Debug: 2240 11838 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr10 (valid=0) Debug: 2241 11842 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr11 Debug: 2242 11846 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr955 Debug: 2243 11852 riscv-013.c:800 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 2244 11860 riscv-013.c:1504 register_read_direct(): {0} csr955 = 0x0 Debug: 2245 11865 riscv.c:3539 riscv_get_register(): [esp32c3] csr955: 0 Debug: 2246 11868 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr11 (valid=0) Debug: 2247 11872 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr12 Debug: 2248 11875 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr956 Debug: 2249 11881 riscv-013.c:800 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc Debug: 2250 11888 riscv-013.c:1504 register_read_direct(): {0} csr956 = 0x0 Debug: 2251 11891 riscv.c:3539 riscv_get_register(): [esp32c3] csr956: 0 Debug: 2252 11896 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr12 (valid=0) Debug: 2253 11900 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr13 Debug: 2254 11903 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr957 Debug: 2255 11907 riscv-013.c:800 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 2256 11917 riscv-013.c:1504 register_read_direct(): {0} csr957 = 0x0 Debug: 2257 11922 riscv.c:3539 riscv_get_register(): [esp32c3] csr957: 0 Debug: 2258 11926 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr13 (valid=0) Debug: 2259 11932 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr14 Debug: 2260 11935 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr958 Debug: 2261 11939 riscv-013.c:800 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 2262 11949 riscv-013.c:1504 register_read_direct(): {0} csr958 = 0x0 Debug: 2263 11952 riscv.c:3539 riscv_get_register(): [esp32c3] csr958: 0 Debug: 2264 11955 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr14 (valid=0) Debug: 2265 11961 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr15 Debug: 2266 11965 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr959 Debug: 2267 11970 riscv-013.c:800 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 2268 11981 riscv-013.c:1504 register_read_direct(): {0} csr959 = 0x0 Debug: 2269 11986 riscv.c:3539 riscv_get_register(): [esp32c3] csr959: 0 Debug: 2270 11991 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr15 (valid=0) Debug: 2271 11996 esp_riscv.c:316 esp_riscv_start_algorithm(): save tselect Debug: 2272 11999 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect Debug: 2273 12003 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 2274 12013 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0 Debug: 2275 12018 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0 Debug: 2276 12023 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tselect (valid=0) Debug: 2277 12027 esp_riscv.c:316 esp_riscv_start_algorithm(): save tdata1 Debug: 2278 12031 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1 Debug: 2279 12035 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 2280 12043 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000 Debug: 2281 12047 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 23e00000 Debug: 2282 12050 riscv.c:3893 register_get(): [esp32c3] read 0x23e00000 from tdata1 (valid=0) Debug: 2283 12055 esp_riscv.c:316 esp_riscv_start_algorithm(): save tdata2 Debug: 2284 12058 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata2 Debug: 2285 12064 riscv-013.c:800 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 2286 12075 riscv-013.c:1504 register_read_direct(): {0} tdata2 = 0x0 Debug: 2287 12079 riscv.c:3539 riscv_get_register(): [esp32c3] tdata2: 0 Debug: 2288 12082 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tdata2 (valid=0) Debug: 2289 12087 esp_riscv.c:316 esp_riscv_start_algorithm(): save tcontrol Debug: 2290 12090 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1957 Debug: 2291 12095 riscv-013.c:800 execute_abstract_command(): command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5 Debug: 2292 12104 riscv-013.c:1504 register_read_direct(): {0} csr1957 = 0x0 Debug: 2293 12109 riscv.c:3539 riscv_get_register(): [esp32c3] csr1957: 0 Debug: 2294 12113 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tcontrol (valid=0) Debug: 2295 12118 esp_riscv.c:316 esp_riscv_start_algorithm(): save dcsr Debug: 2296 12121 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dcsr Debug: 2297 12125 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 2298 12135 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 2299 12139 riscv.c:3539 riscv_get_register(): [esp32c3] dcsr: 4000b0c3 Debug: 2300 12142 riscv.c:3893 register_get(): [esp32c3] read 0x4000b0c3 from dcsr (valid=1) Debug: 2301 12146 esp_riscv.c:316 esp_riscv_start_algorithm(): save dpc Debug: 2302 12150 riscv.c:3522 riscv_get_register(): [esp32c3] dpc: 40000000 (cached) Debug: 2303 12154 riscv.c:3893 register_get(): [esp32c3] read 0x40000000 from dpc (valid=1) Debug: 2304 12158 esp_riscv.c:316 esp_riscv_start_algorithm(): save dscratch0 Debug: 2305 12162 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dscratch0 Debug: 2306 12168 riscv-013.c:800 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 2307 12179 riscv-013.c:1504 register_read_direct(): {0} dscratch0 = 0x0 Debug: 2308 12183 riscv.c:3539 riscv_get_register(): [esp32c3] dscratch0: 0 Debug: 2309 12187 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from dscratch0 (valid=1) Debug: 2310 12191 esp_riscv.c:316 esp_riscv_start_algorithm(): save dscratch1 Debug: 2311 12194 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1971 Debug: 2312 12200 riscv-013.c:800 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 2313 12207 riscv-013.c:1504 register_read_direct(): {0} csr1971 = 0x0 Debug: 2314 12213 riscv.c:3539 riscv_get_register(): [esp32c3] csr1971: 0 Debug: 2315 12216 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from dscratch1 (valid=0) Debug: 2316 12220 esp_riscv.c:316 esp_riscv_start_algorithm(): save hpmcounter16 Debug: 2317 12224 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr3088 Debug: 2318 12230 riscv-013.c:800 execute_abstract_command(): command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10 Debug: 2319 12238 riscv-013.c:1504 register_read_direct(): {0} csr3088 = 0x3 Debug: 2320 12243 riscv.c:3539 riscv_get_register(): [esp32c3] csr3088: 3 Debug: 2321 12248 riscv.c:3893 register_get(): [esp32c3] read 0x00000003 from hpmcounter16 (valid=0) Debug: 2322 12253 esp_riscv.c:316 esp_riscv_start_algorithm(): save priv Debug: 2323 12257 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register priv Debug: 2324 12262 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 2325 12273 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 2326 12278 riscv.c:3539 riscv_get_register(): [esp32c3] priv: 3 Debug: 2327 12281 riscv.c:3893 register_get(): [esp32c3] read 0x03 from priv (valid=0) Debug: 2328 12285 esp_riscv.c:345 esp_riscv_start_algorithm(): set sp Debug: 2329 12288 riscv.c:3906 register_set(): [esp32c3] write 0x3fc84810 to sp (valid=1) Debug: 2330 12294 riscv.c:3482 riscv_set_register(): [esp32c3] sp <- 3fc84810 Debug: 2331 12298 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc84810 to register sp Debug: 2332 12304 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fc84810 Debug: 2333 12312 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 2334 12321 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x3fc84810 to sp valid=1 Debug: 2335 12325 esp_riscv.c:345 esp_riscv_start_algorithm(): set a7 Debug: 2336 12329 riscv.c:3906 register_set(): [esp32c3] write 0x403816e4 to a7 (valid=1) Debug: 2337 12332 riscv.c:3482 riscv_set_register(): [esp32c3] a7 <- 403816e4 Debug: 2338 12336 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x403816e4 to register a7 Debug: 2339 12341 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x403816e4 Debug: 2340 12346 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 2341 12353 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x403816e4 to a7 valid=1 Debug: 2342 12359 esp_riscv.c:345 esp_riscv_start_algorithm(): set a0 Debug: 2343 12363 riscv.c:3906 register_set(): [esp32c3] write 0x00000004 to a0 (valid=1) Debug: 2344 12368 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 4 Debug: 2345 12372 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a0 Debug: 2346 12377 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x4 Debug: 2347 12381 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 2348 12391 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4 to a0 valid=1 Debug: 2349 12395 riscv.c:3294 riscv_interrupts_disable(): Disabling Interrupts Debug: 2350 12398 riscv.c:3522 riscv_get_register(): [esp32c3] mstatus: 201800 (cached) Debug: 2351 12403 riscv.c:3893 register_get(): [esp32c3] read 0x00201800 from mstatus (valid=1) Debug: 2352 12407 riscv.c:3906 register_set(): [esp32c3] write 0x00201800 to mstatus (valid=1) Debug: 2353 12411 riscv.c:3482 riscv_set_register(): [esp32c3] mstatus <- 201800 Debug: 2354 12416 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x201800 to register mstatus Debug: 2355 12422 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x201800 Debug: 2356 12427 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 2357 12437 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x201800 to mstatus valid=0 Debug: 2358 12443 esp_riscv.c:382 esp_riscv_start_algorithm(): resume at 0x40381d0c Debug: 2359 12449 riscv.c:1472 riscv_resume(): handle_breakpoints=0 Debug: 2360 12453 riscv.c:1399 resume_prep(): [0] Debug: 2361 12455 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 40381d0c Debug: 2362 12458 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40381d0c to register pc Debug: 2363 12463 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40381d0c Debug: 2364 12469 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40381d0c Debug: 2365 12473 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 2366 12484 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 2367 12491 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381d0c Debug: 2368 12495 riscv-013.c:4124 riscv013_set_register(): [0] actual DPC written: 0x0000000040381d0c Debug: 2369 12500 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40381d0c to pc valid=0 Debug: 2370 12504 riscv.c:1289 riscv_resume_prep_all_harts(): [esp32c3] prep hart Debug: 2371 12508 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 2372 12514 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100f @0 Debug: 2373 12518 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 2374 12521 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0xf @1 Debug: 2375 12525 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 2376 12531 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 2377 12536 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 2378 12547 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 2379 12555 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 2380 12559 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3 Debug: 2381 12563 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr Debug: 2382 12568 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 2383 12572 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 2384 12583 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0 Debug: 2385 12588 riscv.c:1300 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped Debug: 2386 12593 riscv.c:1424 resume_prep(): [0] mark as prepped Debug: 2387 12596 riscv.c:3277 riscv_resume_go_all_harts(): [esp32c3] resuming hart Debug: 2388 12601 riscv-013.c:4190 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 2389 12604 riscv-013.c:4815 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0) Debug: 2390 12612 riscv.c:3400 riscv_invalidate_register_cache(): [0] Debug: 2391 12616 target.c:1857 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c3 Debug: 2392 12624 esp32c3.c:115 esp32c3_handle_target_event(): 18 Debug: 2393 12627 esp_riscv.c:276 esp_riscv_handle_target_event(): 18 Debug: 2394 12631 esp_algorithm.c:220 algorithm_run(): Wait algorithm completion Debug: 2395 12636 riscv.c:2078 riscv_poll_hart(): triggered a halt Debug: 2396 12641 riscv.c:2258 riscv_openocd_poll(): hart 0 halted Debug: 2397 12645 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 2398 12654 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043 Debug: 2399 12658 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x1 Debug: 2400 12662 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=1 Debug: 2401 12666 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc Debug: 2402 12670 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 2403 12680 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381d0e Debug: 2404 12685 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381d0e Debug: 2405 12690 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40381d0e Debug: 2406 12693 esp_riscv.c:524 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40381d0a Debug: 2407 12704 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus. Debug: 2408 12711 esp_riscv.c:524 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40381d0e Debug: 2409 12720 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus. Debug: 2410 12727 esp_riscv.c:524 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40381d12 Debug: 2411 12737 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus. Debug: 2412 12743 riscv_semihosting.c:109 riscv_semihosting(): check 9882bd19 08339002 78b341e8 from 0x40381d0e-4 Debug: 2413 12749 riscv_semihosting.c:113 riscv_semihosting(): -> NONE (no magic) Debug: 2414 12753 target.c:1857 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 2415 12757 esp32c3.c:115 esp32c3_handle_target_event(): 0 Debug: 2416 12760 esp_riscv.c:276 esp_riscv_handle_target_event(): 0 Debug: 2417 12765 target.c:1857 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 2418 12769 target.c:5148 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable

Debug: 2419 12775 command.c:166 script_debug(): command - command mode Debug: 2420 12781 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1 Debug: 2421 12787 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 2422 12796 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2423 12800 command.c:166 script_debug(): command - mww 0x6001F048 0 Debug: 2424 12805 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 2425 12814 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2426 12818 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1 Debug: 2427 12824 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 2428 12830 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2429 12835 command.c:166 script_debug(): command - mww 0x60020048 0 Debug: 2430 12840 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 2431 12846 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2432 12852 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1 Debug: 2433 12860 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 2434 12867 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2435 12873 command.c:166 script_debug(): command - mww 0x60008090 0 Debug: 2436 12878 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 2437 12886 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2438 12891 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A Debug: 2439 12897 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 2440 12906 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2441 12911 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000 Debug: 2442 12918 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 2443 12924 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2444 12929 esp32c3.c:115 esp32c3_handle_target_event(): 1 Debug: 2445 12931 esp_riscv.c:276 esp_riscv_handle_target_event(): 1 Debug: 2446 12936 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc Debug: 2447 12941 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 2448 12951 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381d0e Debug: 2449 12956 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381d0e Debug: 2450 12962 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40381d0e Debug: 2451 12966 riscv.c:3893 register_get(): [esp32c3] read 0x40381d0e from pc (valid=0) Debug: 2452 12971 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0 Debug: 2453 12978 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 2454 12987 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x0 Debug: 2455 12991 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 0 Debug: 2456 12995 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1) Debug: 2457 13000 esp_riscv.c:460 esp_riscv_wait_algorithm(): Read mem params Debug: 2458 13004 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore ra Debug: 2459 13007 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to ra (valid=0) Debug: 2460 13011 riscv.c:3482 riscv_set_register(): [esp32c3] ra <- 0 Debug: 2461 13015 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register ra Debug: 2462 13019 riscv-013.c:1315 register_write_direct(): {0} ra <- 0x0 Debug: 2463 13022 riscv-013.c:800 execute_abstract_command(): command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001 Debug: 2464 13033 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to ra valid=1 Debug: 2465 13036 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore sp Debug: 2466 13039 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to sp (valid=0) Debug: 2467 13045 riscv.c:3482 riscv_set_register(): [esp32c3] sp <- 0 Debug: 2468 13048 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register sp Debug: 2469 13051 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x0 Debug: 2470 13056 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 2471 13066 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to sp valid=1 Debug: 2472 13071 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore gp Debug: 2473 13077 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to gp (valid=0) Debug: 2474 13082 riscv.c:3482 riscv_set_register(): [esp32c3] gp <- 0 Debug: 2475 13086 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register gp Debug: 2476 13092 riscv-013.c:1315 register_write_direct(): {0} gp <- 0x0 Debug: 2477 13096 riscv-013.c:800 execute_abstract_command(): command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003 Debug: 2478 13106 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to gp valid=1 Debug: 2479 13111 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tp Debug: 2480 13115 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tp (valid=0) Debug: 2481 13120 riscv.c:3482 riscv_set_register(): [esp32c3] tp <- 0 Debug: 2482 13125 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tp Debug: 2483 13131 riscv-013.c:1315 register_write_direct(): {0} tp <- 0x0 Debug: 2484 13135 riscv-013.c:800 execute_abstract_command(): command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004 Debug: 2485 13147 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tp valid=1 Debug: 2486 13150 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t0 Debug: 2487 13154 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t0 (valid=0) Debug: 2488 13159 riscv.c:3482 riscv_set_register(): [esp32c3] t0 <- 0 Debug: 2489 13162 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t0 Debug: 2490 13166 riscv-013.c:1315 register_write_direct(): {0} t0 <- 0x0 Debug: 2491 13171 riscv-013.c:800 execute_abstract_command(): command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005 Debug: 2492 13180 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t0 valid=1 Debug: 2493 13186 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t1 Debug: 2494 13189 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t1 (valid=0) Debug: 2495 13193 riscv.c:3482 riscv_set_register(): [esp32c3] t1 <- 0 Debug: 2496 13197 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t1 Debug: 2497 13201 riscv-013.c:1315 register_write_direct(): {0} t1 <- 0x0 Debug: 2498 13205 riscv-013.c:800 execute_abstract_command(): command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006 Debug: 2499 13218 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t1 valid=1 Debug: 2500 13222 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t2 Debug: 2501 13227 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t2 (valid=0) Debug: 2502 13233 riscv.c:3482 riscv_set_register(): [esp32c3] t2 <- 0 Debug: 2503 13236 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t2 Debug: 2504 13240 riscv-013.c:1315 register_write_direct(): {0} t2 <- 0x0 Debug: 2505 13244 riscv-013.c:800 execute_abstract_command(): command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007 Debug: 2506 13255 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t2 valid=1 Debug: 2507 13259 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore fp Debug: 2508 13263 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to fp (valid=0) Debug: 2509 13267 riscv.c:3482 riscv_set_register(): [esp32c3] s0 <- 0 Debug: 2510 13270 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s0 Debug: 2511 13275 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0 Debug: 2512 13280 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 2513 13288 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to fp valid=1 Debug: 2514 13293 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s1 Debug: 2515 13298 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s1 (valid=0) Debug: 2516 13303 riscv.c:3482 riscv_set_register(): [esp32c3] s1 <- 0 Debug: 2517 13306 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s1 Debug: 2518 13311 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x0 Debug: 2519 13315 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 2520 13324 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s1 valid=1 Debug: 2521 13331 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a0 Debug: 2522 13335 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a0 (valid=1) Debug: 2523 13340 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 0 Debug: 2524 13347 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a0 Debug: 2525 13350 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0 Debug: 2526 13354 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 2527 13365 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1 Debug: 2528 13370 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a1 Debug: 2529 13375 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a1 (valid=0) Debug: 2530 13379 riscv.c:3482 riscv_set_register(): [esp32c3] a1 <- 0 Debug: 2531 13382 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a1 Debug: 2532 13386 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0x0 Debug: 2533 13390 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 2534 13400 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a1 valid=1 Debug: 2535 13403 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a2 Debug: 2536 13407 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a2 (valid=0) Debug: 2537 13411 riscv.c:3482 riscv_set_register(): [esp32c3] a2 <- 0 Debug: 2538 13414 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a2 Debug: 2539 13418 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x0 Debug: 2540 13423 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 2541 13433 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a2 valid=1 Debug: 2542 13436 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a3 Debug: 2543 13440 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a3 (valid=0) Debug: 2544 13446 riscv.c:3482 riscv_set_register(): [esp32c3] a3 <- 0 Debug: 2545 13449 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a3 Debug: 2546 13453 riscv-013.c:1315 register_write_direct(): {0} a3 <- 0x0 Debug: 2547 13458 riscv-013.c:800 execute_abstract_command(): command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d Debug: 2548 13468 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a3 valid=1 Debug: 2549 13473 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a4 Debug: 2550 13476 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a4 (valid=0) Debug: 2551 13481 riscv.c:3482 riscv_set_register(): [esp32c3] a4 <- 0 Debug: 2552 13484 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a4 Debug: 2553 13489 riscv-013.c:1315 register_write_direct(): {0} a4 <- 0x0 Debug: 2554 13492 riscv-013.c:800 execute_abstract_command(): command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e Debug: 2555 13501 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a4 valid=1 Debug: 2556 13506 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a5 Debug: 2557 13510 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a5 (valid=0) Debug: 2558 13515 riscv.c:3482 riscv_set_register(): [esp32c3] a5 <- 0 Debug: 2559 13520 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a5 Debug: 2560 13525 riscv-013.c:1315 register_write_direct(): {0} a5 <- 0x0 Debug: 2561 13529 riscv-013.c:800 execute_abstract_command(): command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f Debug: 2562 13537 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a5 valid=1 Debug: 2563 13542 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a6 Debug: 2564 13548 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a6 (valid=0) Debug: 2565 13551 riscv.c:3482 riscv_set_register(): [esp32c3] a6 <- 0 Debug: 2566 13554 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a6 Debug: 2567 13558 riscv-013.c:1315 register_write_direct(): {0} a6 <- 0x0 Debug: 2568 13563 riscv-013.c:800 execute_abstract_command(): command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010 Debug: 2569 13571 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a6 valid=1 Debug: 2570 13574 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a7 Debug: 2571 13579 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a7 (valid=0) Debug: 2572 13583 riscv.c:3482 riscv_set_register(): [esp32c3] a7 <- 0 Debug: 2573 13586 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a7 Debug: 2574 13589 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x0 Debug: 2575 13594 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 2576 13604 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a7 valid=1 Debug: 2577 13608 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s2 Debug: 2578 13612 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s2 (valid=0) Debug: 2579 13616 riscv.c:3482 riscv_set_register(): [esp32c3] s2 <- 0 Debug: 2580 13619 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s2 Debug: 2581 13623 riscv-013.c:1315 register_write_direct(): {0} s2 <- 0x0 Debug: 2582 13629 riscv-013.c:800 execute_abstract_command(): command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012 Debug: 2583 13638 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s2 valid=1 Debug: 2584 13644 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s3 Debug: 2585 13648 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s3 (valid=0) Debug: 2586 13653 riscv.c:3482 riscv_set_register(): [esp32c3] s3 <- 0 Debug: 2587 13658 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s3 Debug: 2588 13663 riscv-013.c:1315 register_write_direct(): {0} s3 <- 0x0 Debug: 2589 13667 riscv-013.c:800 execute_abstract_command(): command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013 Debug: 2590 13675 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s3 valid=1 Debug: 2591 13680 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s4 Debug: 2592 13683 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s4 (valid=0) Debug: 2593 13687 riscv.c:3482 riscv_set_register(): [esp32c3] s4 <- 0 Debug: 2594 13692 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s4 Debug: 2595 13696 riscv-013.c:1315 register_write_direct(): {0} s4 <- 0x0 Debug: 2596 13701 riscv-013.c:800 execute_abstract_command(): command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014 Debug: 2597 13711 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s4 valid=1 Debug: 2598 13714 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s5 Debug: 2599 13719 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s5 (valid=0) Debug: 2600 13723 riscv.c:3482 riscv_set_register(): [esp32c3] s5 <- 0 Debug: 2601 13726 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s5 Debug: 2602 13732 riscv-013.c:1315 register_write_direct(): {0} s5 <- 0x0 Debug: 2603 13738 riscv-013.c:800 execute_abstract_command(): command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015 Debug: 2604 13747 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s5 valid=1 Debug: 2605 13752 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s6 Debug: 2606 13755 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s6 (valid=0) Debug: 2607 13759 riscv.c:3482 riscv_set_register(): [esp32c3] s6 <- 0 Debug: 2608 13762 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s6 Debug: 2609 13768 riscv-013.c:1315 register_write_direct(): {0} s6 <- 0x0 Debug: 2610 13772 riscv-013.c:800 execute_abstract_command(): command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016 Debug: 2611 13781 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s6 valid=1 Debug: 2612 13785 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s7 Debug: 2613 13788 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s7 (valid=0) Debug: 2614 13792 riscv.c:3482 riscv_set_register(): [esp32c3] s7 <- 0 Debug: 2615 13795 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s7 Debug: 2616 13800 riscv-013.c:1315 register_write_direct(): {0} s7 <- 0x0 Debug: 2617 13804 riscv-013.c:800 execute_abstract_command(): command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017 Debug: 2618 13815 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s7 valid=1 Debug: 2619 13819 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s8 Debug: 2620 13822 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s8 (valid=0) Debug: 2621 13825 riscv.c:3482 riscv_set_register(): [esp32c3] s8 <- 0 Debug: 2622 13830 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s8 Debug: 2623 13834 riscv-013.c:1315 register_write_direct(): {0} s8 <- 0x0 Debug: 2624 13838 riscv-013.c:800 execute_abstract_command(): command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018 Debug: 2625 13847 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s8 valid=1 Debug: 2626 13850 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s9 Debug: 2627 13853 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s9 (valid=0) Debug: 2628 13857 riscv.c:3482 riscv_set_register(): [esp32c3] s9 <- 0 Debug: 2629 13863 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s9 Debug: 2630 13867 riscv-013.c:1315 register_write_direct(): {0} s9 <- 0x0 Debug: 2631 13871 riscv-013.c:800 execute_abstract_command(): command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019 Debug: 2632 13880 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s9 valid=1 Debug: 2633 13884 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s10 Debug: 2634 13888 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s10 (valid=0) Debug: 2635 13894 riscv.c:3482 riscv_set_register(): [esp32c3] s10 <- 0 Debug: 2636 13897 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s10 Debug: 2637 13901 riscv-013.c:1315 register_write_direct(): {0} s10 <- 0x0 Debug: 2638 13905 riscv-013.c:800 execute_abstract_command(): command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a Debug: 2639 13915 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s10 valid=1 Debug: 2640 13919 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s11 Debug: 2641 13923 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s11 (valid=0) Debug: 2642 13927 riscv.c:3482 riscv_set_register(): [esp32c3] s11 <- 0 Debug: 2643 13930 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s11 Debug: 2644 13934 riscv-013.c:1315 register_write_direct(): {0} s11 <- 0x0 Debug: 2645 13939 riscv-013.c:800 execute_abstract_command(): command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b Debug: 2646 13948 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s11 valid=1 Debug: 2647 13953 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t3 Debug: 2648 13956 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t3 (valid=0) Debug: 2649 13961 riscv.c:3482 riscv_set_register(): [esp32c3] t3 <- 0 Debug: 2650 13965 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t3 Debug: 2651 13971 riscv-013.c:1315 register_write_direct(): {0} t3 <- 0x0 Debug: 2652 13974 riscv-013.c:800 execute_abstract_command(): command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c Debug: 2653 13985 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t3 valid=1 Debug: 2654 13990 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t4 Debug: 2655 13995 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t4 (valid=0) Debug: 2656 14000 riscv.c:3482 riscv_set_register(): [esp32c3] t4 <- 0 Debug: 2657 14003 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t4 Debug: 2658 14007 riscv-013.c:1315 register_write_direct(): {0} t4 <- 0x0 Debug: 2659 14011 riscv-013.c:800 execute_abstract_command(): command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d Debug: 2660 14021 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t4 valid=1 Debug: 2661 14025 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t5 Debug: 2662 14028 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t5 (valid=0) Debug: 2663 14033 riscv.c:3482 riscv_set_register(): [esp32c3] t5 <- 0 Debug: 2664 14036 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t5 Debug: 2665 14040 riscv-013.c:1315 register_write_direct(): {0} t5 <- 0x0 Debug: 2666 14045 riscv-013.c:800 execute_abstract_command(): command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e Debug: 2667 14054 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t5 valid=1 Debug: 2668 14058 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t6 Debug: 2669 14064 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t6 (valid=0) Debug: 2670 14069 riscv.c:3482 riscv_set_register(): [esp32c3] t6 <- 0 Debug: 2671 14073 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t6 Debug: 2672 14079 riscv-013.c:1315 register_write_direct(): {0} t6 <- 0x0 Debug: 2673 14083 riscv-013.c:800 execute_abstract_command(): command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f Debug: 2674 14091 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t6 valid=1 Debug: 2675 14096 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pc Debug: 2676 14099 riscv.c:3906 register_set(): [esp32c3] write 0x40000000 to pc (valid=0) Debug: 2677 14103 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 40000000 Debug: 2678 14106 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40000000 to register pc Debug: 2679 14112 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40000000 Debug: 2680 14117 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40000000 Debug: 2681 14122 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 2682 14132 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 2683 14141 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40000000 Debug: 2684 14145 riscv-013.c:4124 riscv013_set_register(): [0] actual DPC written: 0x0000000040000000 Debug: 2685 14150 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40000000 to pc valid=0 Debug: 2686 14154 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mstatus Debug: 2687 14159 riscv.c:3906 register_set(): [esp32c3] write 0x00201800 to mstatus (valid=0) Debug: 2688 14165 riscv.c:3482 riscv_set_register(): [esp32c3] mstatus <- 201800 Debug: 2689 14169 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x201800 to register mstatus Debug: 2690 14176 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x201800 Debug: 2691 14182 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 2692 14191 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x201800 to mstatus valid=0 Debug: 2693 14196 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore misa Debug: 2694 14199 riscv.c:3906 register_set(): [esp32c3] write 0x40101104 to misa (valid=0) Debug: 2695 14204 riscv.c:3482 riscv_set_register(): [esp32c3] misa <- 40101104 Debug: 2696 14208 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40101104 to register misa Debug: 2697 14214 riscv-013.c:1315 register_write_direct(): {0} misa <- 0x40101104 Debug: 2698 14218 riscv-013.c:800 execute_abstract_command(): command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301 Debug: 2699 14226 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40101104 to misa valid=0 Debug: 2700 14230 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mtvec Debug: 2701 14234 riscv.c:3906 register_set(): [esp32c3] write 0x00000001 to mtvec (valid=0) Debug: 2702 14240 riscv.c:3482 riscv_set_register(): [esp32c3] csr773 <- 1 Debug: 2703 14244 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register csr773 Debug: 2704 14250 riscv-013.c:1315 register_write_direct(): {0} csr773 <- 0x1 Debug: 2705 14254 riscv-013.c:800 execute_abstract_command(): command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305 Debug: 2706 14264 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to mtvec valid=0 Debug: 2707 14269 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mscratch Debug: 2708 14273 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mscratch (valid=0) Debug: 2709 14277 riscv.c:3482 riscv_set_register(): [esp32c3] csr832 <- 0 Debug: 2710 14283 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr832 Debug: 2711 14287 riscv-013.c:1315 register_write_direct(): {0} csr832 <- 0x0 Debug: 2712 14290 riscv-013.c:800 execute_abstract_command(): command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340 Debug: 2713 14300 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mscratch valid=0 Debug: 2714 14304 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mepc Debug: 2715 14308 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mepc (valid=0) Debug: 2716 14313 riscv.c:3482 riscv_set_register(): [esp32c3] mepc <- 0 Debug: 2717 14316 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register mepc Debug: 2718 14320 riscv-013.c:1315 register_write_direct(): {0} mepc <- 0x0 Debug: 2719 14324 riscv-013.c:800 execute_abstract_command(): command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341 Debug: 2720 14334 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mepc valid=0 Debug: 2721 14338 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mcause Debug: 2722 14344 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mcause (valid=0) Debug: 2723 14349 riscv.c:3482 riscv_set_register(): [esp32c3] mcause <- 0 Debug: 2724 14352 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register mcause Debug: 2725 14356 riscv-013.c:1315 register_write_direct(): {0} mcause <- 0x0 Debug: 2726 14362 riscv-013.c:800 execute_abstract_command(): command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342 Debug: 2727 14372 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mcause valid=0 Debug: 2728 14378 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mtval Debug: 2729 14381 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mtval (valid=0) Debug: 2730 14385 riscv.c:3482 riscv_set_register(): [esp32c3] csr835 <- 0 Debug: 2731 14390 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr835 Debug: 2732 14394 riscv-013.c:1315 register_write_direct(): {0} csr835 <- 0x0 Debug: 2733 14398 riscv-013.c:800 execute_abstract_command(): command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343 Debug: 2734 14408 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mtval valid=0 Debug: 2735 14412 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg0 Debug: 2736 14415 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg0 (valid=0) Debug: 2737 14419 riscv.c:3482 riscv_set_register(): [esp32c3] csr928 <- 0 Debug: 2738 14423 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr928 Debug: 2739 14427 riscv-013.c:1315 register_write_direct(): {0} csr928 <- 0x0 Debug: 2740 14433 riscv-013.c:800 execute_abstract_command(): command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0 Debug: 2741 14442 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg0 valid=0 Debug: 2742 14447 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg1 Debug: 2743 14450 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg1 (valid=0) Debug: 2744 14455 riscv.c:3482 riscv_set_register(): [esp32c3] csr929 <- 0 Debug: 2745 14458 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr929 Debug: 2746 14462 riscv-013.c:1315 register_write_direct(): {0} csr929 <- 0x0 Debug: 2747 14466 riscv-013.c:800 execute_abstract_command(): command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1 Debug: 2748 14475 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg1 valid=0 Debug: 2749 14480 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg2 Debug: 2750 14483 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg2 (valid=0) Debug: 2751 14488 riscv.c:3482 riscv_set_register(): [esp32c3] csr930 <- 0 Debug: 2752 14491 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr930 Debug: 2753 14496 riscv-013.c:1315 register_write_direct(): {0} csr930 <- 0x0 Debug: 2754 14503 riscv-013.c:800 execute_abstract_command(): command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2 Debug: 2755 14513 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg2 valid=0 Debug: 2756 14517 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg3 Debug: 2757 14521 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg3 (valid=0) Debug: 2758 14525 riscv.c:3482 riscv_set_register(): [esp32c3] csr931 <- 0 Debug: 2759 14529 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr931 Debug: 2760 14534 riscv-013.c:1315 register_write_direct(): {0} csr931 <- 0x0 Debug: 2761 14539 riscv-013.c:800 execute_abstract_command(): command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3 Debug: 2762 14547 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg3 valid=0 Debug: 2763 14551 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr0 Debug: 2764 14554 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr0 (valid=0) Debug: 2765 14558 riscv.c:3482 riscv_set_register(): [esp32c3] csr944 <- 0 Debug: 2766 14563 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr944 Debug: 2767 14567 riscv-013.c:1315 register_write_direct(): {0} csr944 <- 0x0 Debug: 2768 14571 riscv-013.c:800 execute_abstract_command(): command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0 Debug: 2769 14583 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr0 valid=0 Debug: 2770 14587 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr1 Debug: 2771 14589 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr1 (valid=0) Debug: 2772 14595 riscv.c:3482 riscv_set_register(): [esp32c3] csr945 <- 0 Debug: 2773 14598 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr945 Debug: 2774 14602 riscv-013.c:1315 register_write_direct(): {0} csr945 <- 0x0 Debug: 2775 14606 riscv-013.c:800 execute_abstract_command(): command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1 Debug: 2776 14616 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr1 valid=0 Debug: 2777 14622 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr2 Debug: 2778 14627 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr2 (valid=0) Debug: 2779 14631 riscv.c:3482 riscv_set_register(): [esp32c3] csr946 <- 0 Debug: 2780 14634 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr946 Debug: 2781 14638 riscv-013.c:1315 register_write_direct(): {0} csr946 <- 0x0 Debug: 2782 14644 riscv-013.c:800 execute_abstract_command(): command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2 Debug: 2783 14654 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr2 valid=0 Debug: 2784 14659 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr3 Debug: 2785 14662 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr3 (valid=0) Debug: 2786 14666 riscv.c:3482 riscv_set_register(): [esp32c3] csr947 <- 0 Debug: 2787 14671 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr947 Debug: 2788 14675 riscv-013.c:1315 register_write_direct(): {0} csr947 <- 0x0 Debug: 2789 14680 riscv-013.c:800 execute_abstract_command(): command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3 Debug: 2790 14688 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr3 valid=0 Debug: 2791 14694 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr4 Debug: 2792 14698 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr4 (valid=0) Debug: 2793 14703 riscv.c:3482 riscv_set_register(): [esp32c3] csr948 <- 0 Debug: 2794 14706 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr948 Debug: 2795 14710 riscv-013.c:1315 register_write_direct(): {0} csr948 <- 0x0 Debug: 2796 14714 riscv-013.c:800 execute_abstract_command(): command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4 Debug: 2797 14728 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr4 valid=0 Debug: 2798 14733 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr5 Debug: 2799 14737 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr5 (valid=0) Debug: 2800 14741 riscv.c:3482 riscv_set_register(): [esp32c3] csr949 <- 0 Debug: 2801 14745 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr949 Debug: 2802 14749 riscv-013.c:1315 register_write_direct(): {0} csr949 <- 0x0 Debug: 2803 14753 riscv-013.c:800 execute_abstract_command(): command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5 Debug: 2804 14762 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr5 valid=0 Debug: 2805 14767 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr6 Debug: 2806 14770 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr6 (valid=0) Debug: 2807 14774 riscv.c:3482 riscv_set_register(): [esp32c3] csr950 <- 0 Debug: 2808 14778 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr950 Debug: 2809 14783 riscv-013.c:1315 register_write_direct(): {0} csr950 <- 0x0 Debug: 2810 14787 riscv-013.c:800 execute_abstract_command(): command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6 Debug: 2811 14795 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr6 valid=0 Debug: 2812 14800 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr7 Debug: 2813 14804 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr7 (valid=0) Debug: 2814 14808 riscv.c:3482 riscv_set_register(): [esp32c3] csr951 <- 0 Debug: 2815 14811 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr951 Debug: 2816 14816 riscv-013.c:1315 register_write_direct(): {0} csr951 <- 0x0 Debug: 2817 14820 riscv-013.c:800 execute_abstract_command(): command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7 Debug: 2818 14831 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr7 valid=0 Debug: 2819 14836 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr8 Debug: 2820 14840 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr8 (valid=0) Debug: 2821 14847 riscv.c:3482 riscv_set_register(): [esp32c3] csr952 <- 0 Debug: 2822 14850 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr952 Debug: 2823 14854 riscv-013.c:1315 register_write_direct(): {0} csr952 <- 0x0 Debug: 2824 14858 riscv-013.c:800 execute_abstract_command(): command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8 Debug: 2825 14869 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr8 valid=0 Debug: 2826 14873 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr9 Debug: 2827 14877 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr9 (valid=0) Debug: 2828 14881 riscv.c:3482 riscv_set_register(): [esp32c3] csr953 <- 0 Debug: 2829 14884 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr953 Debug: 2830 14888 riscv-013.c:1315 register_write_direct(): {0} csr953 <- 0x0 Debug: 2831 14893 riscv-013.c:800 execute_abstract_command(): command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9 Debug: 2832 14901 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr9 valid=0 Debug: 2833 14905 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr10 Debug: 2834 14910 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr10 (valid=0) Debug: 2835 14914 riscv.c:3482 riscv_set_register(): [esp32c3] csr954 <- 0 Debug: 2836 14918 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr954 Debug: 2837 14922 riscv-013.c:1315 register_write_direct(): {0} csr954 <- 0x0 Debug: 2838 14927 riscv-013.c:800 execute_abstract_command(): command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba Debug: 2839 14934 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr10 valid=0 Debug: 2840 14941 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr11 Debug: 2841 14944 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr11 (valid=0) Debug: 2842 14948 riscv.c:3482 riscv_set_register(): [esp32c3] csr955 <- 0 Debug: 2843 14952 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr955 Debug: 2844 14957 riscv-013.c:1315 register_write_direct(): {0} csr955 <- 0x0 Debug: 2845 14961 riscv-013.c:800 execute_abstract_command(): command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb Debug: 2846 14969 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr11 valid=0 Debug: 2847 14975 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr12 Debug: 2848 14979 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr12 (valid=0) Debug: 2849 14985 riscv.c:3482 riscv_set_register(): [esp32c3] csr956 <- 0 Debug: 2850 14990 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr956 Debug: 2851 14995 riscv-013.c:1315 register_write_direct(): {0} csr956 <- 0x0 Debug: 2852 15000 riscv-013.c:800 execute_abstract_command(): command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc Debug: 2853 15009 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr12 valid=0 Debug: 2854 15014 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr13 Debug: 2855 15018 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr13 (valid=0) Debug: 2856 15022 riscv.c:3482 riscv_set_register(): [esp32c3] csr957 <- 0 Debug: 2857 15025 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr957 Debug: 2858 15030 riscv-013.c:1315 register_write_direct(): {0} csr957 <- 0x0 Debug: 2859 15035 riscv-013.c:800 execute_abstract_command(): command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd Debug: 2860 15043 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr13 valid=0 Debug: 2861 15047 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr14 Debug: 2862 15052 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr14 (valid=0) Debug: 2863 15056 riscv.c:3482 riscv_set_register(): [esp32c3] csr958 <- 0 Debug: 2864 15059 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr958 Debug: 2865 15063 riscv-013.c:1315 register_write_direct(): {0} csr958 <- 0x0 Debug: 2866 15068 riscv-013.c:800 execute_abstract_command(): command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be Debug: 2867 15076 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr14 valid=0 Debug: 2868 15081 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr15 Debug: 2869 15085 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr15 (valid=0) Debug: 2870 15089 riscv.c:3482 riscv_set_register(): [esp32c3] csr959 <- 0 Debug: 2871 15092 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr959 Debug: 2872 15097 riscv-013.c:1315 register_write_direct(): {0} csr959 <- 0x0 Debug: 2873 15101 riscv-013.c:800 execute_abstract_command(): command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf Debug: 2874 15112 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr15 valid=0 Debug: 2875 15118 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tselect Debug: 2876 15122 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tselect (valid=0) Debug: 2877 15129 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0 Debug: 2878 15132 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect Debug: 2879 15136 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0 Debug: 2880 15140 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 2881 15150 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0 Debug: 2882 15155 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tdata1 Debug: 2883 15162 riscv.c:3906 register_set(): [esp32c3] write 0x23e00000 to tdata1 (valid=0) Debug: 2884 15167 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 23e00000 Debug: 2885 15172 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x23e00000 to register tdata1 Debug: 2886 15178 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x23e00000 Debug: 2887 15182 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1 Debug: 2888 15191 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x23e00000 to tdata1 valid=0 Debug: 2889 15196 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tdata2 Debug: 2890 15199 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tdata2 (valid=0) Debug: 2891 15203 riscv.c:3482 riscv_set_register(): [esp32c3] tdata2 <- 0 Debug: 2892 15207 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tdata2 Debug: 2893 15212 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x0 Debug: 2894 15217 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2 Debug: 2895 15228 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata2 valid=0 Debug: 2896 15232 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tcontrol Debug: 2897 15238 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tcontrol (valid=0) Debug: 2898 15242 riscv.c:3482 riscv_set_register(): [esp32c3] csr1957 <- 0 Debug: 2899 15246 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr1957 Debug: 2900 15250 riscv-013.c:1315 register_write_direct(): {0} csr1957 <- 0x0 Debug: 2901 15255 riscv-013.c:800 execute_abstract_command(): command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5 Debug: 2902 15264 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tcontrol valid=0 Debug: 2903 15268 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dcsr Debug: 2904 15273 riscv.c:3906 register_set(): [esp32c3] write 0x4000b0c3 to dcsr (valid=0) Debug: 2905 15277 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3 Debug: 2906 15281 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr Debug: 2907 15286 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 2908 15290 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 2909 15299 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0 Debug: 2910 15304 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dpc Debug: 2911 15307 riscv.c:3906 register_set(): [esp32c3] write 0x40000000 to dpc (valid=0) Debug: 2912 15312 riscv.c:3482 riscv_set_register(): [esp32c3] dpc <- 40000000 Debug: 2913 15318 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40000000 to register dpc Debug: 2914 15322 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40000000 Debug: 2915 15327 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 2916 15338 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40000000 to dpc valid=1 Debug: 2917 15342 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dscratch0 Debug: 2918 15345 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to dscratch0 (valid=0) Debug: 2919 15351 riscv.c:3482 riscv_set_register(): [esp32c3] dscratch0 <- 0 Debug: 2920 15354 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register dscratch0 Debug: 2921 15358 riscv-013.c:1315 register_write_direct(): {0} dscratch0 <- 0x0 Debug: 2922 15363 riscv-013.c:800 execute_abstract_command(): command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2 Debug: 2923 15371 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch0 valid=0 Debug: 2924 15375 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dscratch1 Debug: 2925 15380 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to dscratch1 (valid=0) Debug: 2926 15385 riscv.c:3482 riscv_set_register(): [esp32c3] csr1971 <- 0 Debug: 2927 15389 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr1971 Debug: 2928 15394 riscv-013.c:1315 register_write_direct(): {0} csr1971 <- 0x0 Debug: 2929 15399 riscv-013.c:800 execute_abstract_command(): command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3 Debug: 2930 15408 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch1 valid=0 Debug: 2931 15415 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore hpmcounter16 Debug: 2932 15419 riscv.c:3906 register_set(): [esp32c3] write 0x00000003 to hpmcounter16 (valid=0) Debug: 2933 15424 riscv.c:3482 riscv_set_register(): [esp32c3] csr3088 <- 3 Debug: 2934 15430 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register csr3088 Debug: 2935 15434 riscv-013.c:1315 register_write_direct(): {0} csr3088 <- 0x3 Debug: 2936 15439 riscv-013.c:800 execute_abstract_command(): command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10 Debug: 2937 15450 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x3 to hpmcounter16 valid=0 Debug: 2938 15454 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore priv Debug: 2939 15457 riscv.c:3906 register_set(): [esp32c3] write 0x03 to priv (valid=0) Debug: 2940 15462 riscv.c:3482 riscv_set_register(): [esp32c3] priv <- 3 Debug: 2941 15465 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register priv Debug: 2942 15469 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 2943 15479 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 2944 15483 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 2945 15488 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 2946 15498 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x3 to priv valid=0 Debug: 2947 15502 esp_algorithm.c:248 algorithm_run(): Got algorithm RC 0x0 Debug: 2948 15507 target.c:2203 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381d0c Debug: 2949 15512 target.c:1983 print_wa_layout(): 0x40380000-0x40381d0b (7436 bytes) Debug: 2950 15516 target.c:1983 print_wa_layout(): 0x40381d0c-0x40383fff (8948 bytes) Debug: 2951 15521 target.c:2203 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3fc84428 Debug: 2952 15529 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fc84427 (1064 bytes) Debug: 2953 15533 target.c:1983 print_wa_layout(): 0x3fc84428-0x3fca3fff (130008 bytes) Debug: 2954 15538 target.c:2203 target_free_working_area_restore(): freed 7436 bytes of working area at address 0x40380000 Debug: 2955 15545 target.c:1983 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes) Debug: 2956 15549 target.c:2203 target_free_working_area_restore(): freed 1064 bytes of working area at address 0x3fc84000 Debug: 2957 15555 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fca3fff (131072 bytes) Error: 2958 15559 esp_flash.c:344 esp_flash_get_size(): Failed to get flash size! Debug: 2959 15564 esp_flash.c:345 esp_flash_get_size(): esp_flash_get_size size 0x0 Debug: 2960 15570 esp_flash.c:241 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 2961 15574 esp_algorithm.c:313 algorithm_load_func_image(): stub: base 0x0, start 0x403816e4, 2 sections Debug: 2962 15581 esp_algorithm.c:320 algorithm_load_func_image(): addr 0x00000000, sz 7436, flags 1 Debug: 2963 15587 target.c:2116 alloc_working_area_try_do(): allocated new working area of 7436 bytes at address 0x40380000 Debug: 2964 15592 target.c:1983 print_wa_layout(): * 0x40380000-0x40381d0b (7436 bytes) Debug: 2965 15597 target.c:1983 print_wa_layout(): 0x40381d0c-0x40383fff (8948 bytes) Debug: 2966 15601 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380000 Debug: 2967 15607 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 2968 15614 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 2969 15621 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 2970 15631 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 2971 15637 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2972 15641 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380200 Debug: 2973 15648 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 2974 15657 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 2975 15667 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 2976 15675 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 2977 15684 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2978 15690 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380400 Debug: 2979 15699 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 2980 15707 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 2981 15716 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 2982 15724 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 2983 15732 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2984 15738 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380600 Debug: 2985 15745 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 2986 15751 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 2987 15759 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 2988 15767 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 2989 15775 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2990 15780 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380800 Debug: 2991 15786 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 2992 15795 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 2993 15804 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 2994 15813 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 2995 15821 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 2996 15828 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380a00 Debug: 2997 15835 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 2998 15843 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 2999 15851 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 3000 15859 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 3001 15867 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3002 15873 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380c00 Debug: 3003 15881 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 3004 15887 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 3005 15896 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 3006 15904 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 3007 15914 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3008 15920 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40380e00 Debug: 3009 15928 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 3010 15936 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 3011 15945 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 3012 15953 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 3013 15962 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3014 15968 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40381000 Debug: 3015 15976 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 3016 15983 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 3017 15992 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 3018 15999 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 3019 16006 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3020 16012 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40381200 Debug: 3021 16018 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 3022 16025 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 3023 16032 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 3024 16040 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 3025 16049 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3026 16054 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40381400 Debug: 3027 16060 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 3028 16068 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 3029 16076 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 3030 16086 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 3031 16095 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3032 16101 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40381600 Debug: 3033 16106 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 3034 16114 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 3035 16122 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 3036 16130 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 3037 16137 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3038 16143 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40381800 Debug: 3039 16149 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 3040 16157 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 3041 16166 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 3042 16173 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 3043 16182 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3044 16188 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x40381a00 Debug: 3045 16196 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 3046 16203 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 3047 16214 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 3048 16223 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 3049 16231 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3050 16236 target.c:2466 target_write_buffer(): writing buffer of 268 byte at 0x40381c00 Debug: 3051 16244 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 3052 16252 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 3053 16260 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 3054 16266 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3055 16271 esp_algorithm.c:320 algorithm_load_func_image(): addr 0x00000000, sz 769, flags 0 Debug: 3056 16276 esp_algorithm.c:352 algorithm_load_func_image(): DATA sec size 769 -> 772 Debug: 3057 16280 esp_algorithm.c:357 algorithm_load_func_image(): BSS sec size 289 -> 292 Debug: 3058 16284 target.c:2116 alloc_working_area_try_do(): allocated new working area of 1064 bytes at address 0x3fc84000 Debug: 3059 16290 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fc84427 (1064 bytes) Debug: 3060 16294 target.c:1983 print_wa_layout(): 0x3fc84428-0x3fca3fff (130008 bytes) Debug: 3061 16298 target.c:2466 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000 Debug: 3062 16305 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 3063 16313 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 3064 16320 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 3065 16327 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 3066 16335 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3067 16341 target.c:2466 target_write_buffer(): writing buffer of 257 byte at 0x3fc84200 Debug: 3068 16349 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 3069 16355 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84280 Debug: 3070 16362 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3071 16367 riscv-013.c:2908 mem_should_skip_sysbus(): Skipping mem write via system bus - unsupported size. Debug: 3072 16372 riscv-013.c:3815 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc84300 Debug: 3073 16377 riscv-013.c:800 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 3074 16386 riscv-013.c:1504 register_read_direct(): {0} s0 = 0x0 Debug: 3075 16389 riscv-013.c:800 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 3076 16400 riscv-013.c:1504 register_read_direct(): {0} s1 = 0x0 Debug: 3077 16403 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x00940023) Debug: 3078 16407 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x00140413) Debug: 3079 16414 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 3080 16419 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 3081 16424 riscv-013.c:3872 write_memory_progbuf(): writing until final address 0x000000003fc84301 Debug: 3082 16432 riscv-013.c:3875 write_memory_progbuf(): transferring burst starting at address 0x000000003fc84300 Debug: 3083 16438 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x3fc84300 Debug: 3084 16443 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 3085 16452 riscv-013.c:800 execute_abstract_command(): command=0x271009; access register, size=32, postexec=1, transfer=1, write=1, regno=0x1009 Debug: 3086 16462 batch.c:91 riscv_batch_run(): Ignoring empty batch. Debug: 3087 16467 riscv-013.c:3955 write_memory_progbuf(): successful (partial?) memory write Debug: 3088 16475 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x0 Debug: 3089 16480 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 3090 16489 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0 Debug: 3091 16495 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 3092 16503 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 3093 16510 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 3094 16515 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 3095 16519 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 3096 16524 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 3097 16533 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via program buffer. Debug: 3098 16539 target.c:2116 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3fc84428 Debug: 3099 16545 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fc84427 (1064 bytes) Debug: 3100 16549 target.c:1983 print_wa_layout(): 0x3fc84428-0x3fc84827 (1024 bytes) Debug: 3101 16553 target.c:1983 print_wa_layout(): 0x3fc84828-0x3fca3fff (128984 bytes) Debug: 3102 16558 target.c:2116 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381d0c Debug: 3103 16565 target.c:1983 print_wa_layout(): 0x40380000-0x40381d0b (7436 bytes) Debug: 3104 16571 target.c:1983 print_wa_layout(): * 0x40381d0c-0x40381d0f (4 bytes) Debug: 3105 16575 target.c:1983 print_wa_layout(): 0x40381d10-0x40383fff (8944 bytes) Debug: 3106 16579 target.c:2466 target_write_buffer(): writing buffer of 4 byte at 0x40381d0c Debug: 3107 16584 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381d0c Debug: 3108 16592 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3109 16597 esp_algorithm.c:443 algorithm_load_func_image(): Stub loaded in 1023.25 ms Debug: 3110 16601 esp_riscv_algorithm.c:53 esp_riscv_algo_regs_init_start(): Check stack addr 0x3fc84828 Debug: 3111 16606 esp_riscv_algorithm.c:56 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc84820 Debug: 3112 16611 esp_riscv_algorithm.c:96 esp_riscv_algo_init(): Set arg[0] = 4 (a0) Debug: 3113 16616 esp_algorithm.c:198 algorithm_run(): Algorithm start @ 0x40381d0c, stack 1024 bytes @ 0x3fc84828 Debug: 3114 16623 esp_riscv.c:316 esp_riscv_start_algorithm(): save ra Debug: 3115 16626 riscv.c:3522 riscv_get_register(): [esp32c3] ra: 0 (cached) Debug: 3116 16629 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from ra (valid=1) Debug: 3117 16634 esp_riscv.c:316 esp_riscv_start_algorithm(): save sp Debug: 3118 16637 riscv.c:3522 riscv_get_register(): [esp32c3] sp: 0 (cached) Debug: 3119 16641 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from sp (valid=1) Debug: 3120 16645 esp_riscv.c:316 esp_riscv_start_algorithm(): save gp Debug: 3121 16651 riscv.c:3522 riscv_get_register(): [esp32c3] gp: 0 (cached) Debug: 3122 16655 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from gp (valid=1) Debug: 3123 16661 esp_riscv.c:316 esp_riscv_start_algorithm(): save tp Debug: 3124 16665 riscv.c:3522 riscv_get_register(): [esp32c3] tp: 0 (cached) Debug: 3125 16669 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tp (valid=1) Debug: 3126 16674 esp_riscv.c:316 esp_riscv_start_algorithm(): save t0 Debug: 3127 16678 riscv.c:3522 riscv_get_register(): [esp32c3] t0: 0 (cached) Debug: 3128 16683 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t0 (valid=1) Debug: 3129 16687 esp_riscv.c:316 esp_riscv_start_algorithm(): save t1 Debug: 3130 16690 riscv.c:3522 riscv_get_register(): [esp32c3] t1: 0 (cached) Debug: 3131 16694 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t1 (valid=1) Debug: 3132 16698 esp_riscv.c:316 esp_riscv_start_algorithm(): save t2 Debug: 3133 16701 riscv.c:3522 riscv_get_register(): [esp32c3] t2: 0 (cached) Debug: 3134 16705 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1) Debug: 3135 16708 esp_riscv.c:316 esp_riscv_start_algorithm(): save fp Debug: 3136 16713 riscv.c:3522 riscv_get_register(): [esp32c3] s0: 0 (cached) Debug: 3137 16716 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from fp (valid=1) Debug: 3138 16720 esp_riscv.c:316 esp_riscv_start_algorithm(): save s1 Debug: 3139 16723 riscv.c:3522 riscv_get_register(): [esp32c3] s1: 0 (cached) Debug: 3140 16727 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s1 (valid=1) Debug: 3141 16732 esp_riscv.c:316 esp_riscv_start_algorithm(): save a0 Debug: 3142 16735 riscv.c:3522 riscv_get_register(): [esp32c3] a0: 0 (cached) Debug: 3143 16738 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1) Debug: 3144 16742 esp_riscv.c:316 esp_riscv_start_algorithm(): save a1 Debug: 3145 16747 riscv.c:3522 riscv_get_register(): [esp32c3] a1: 0 (cached) Debug: 3146 16750 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a1 (valid=1) Debug: 3147 16754 esp_riscv.c:316 esp_riscv_start_algorithm(): save a2 Debug: 3148 16757 riscv.c:3522 riscv_get_register(): [esp32c3] a2: 0 (cached) Debug: 3149 16762 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a2 (valid=1) Debug: 3150 16766 esp_riscv.c:316 esp_riscv_start_algorithm(): save a3 Debug: 3151 16769 riscv.c:3522 riscv_get_register(): [esp32c3] a3: 0 (cached) Debug: 3152 16772 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a3 (valid=1) Debug: 3153 16778 esp_riscv.c:316 esp_riscv_start_algorithm(): save a4 Debug: 3154 16781 riscv.c:3522 riscv_get_register(): [esp32c3] a4: 0 (cached) Debug: 3155 16784 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a4 (valid=1) Debug: 3156 16788 esp_riscv.c:316 esp_riscv_start_algorithm(): save a5 Debug: 3157 16792 riscv.c:3522 riscv_get_register(): [esp32c3] a5: 0 (cached) Debug: 3158 16795 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a5 (valid=1) Debug: 3159 16799 esp_riscv.c:316 esp_riscv_start_algorithm(): save a6 Debug: 3160 16802 riscv.c:3522 riscv_get_register(): [esp32c3] a6: 0 (cached) Debug: 3161 16805 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1) Debug: 3162 16811 esp_riscv.c:316 esp_riscv_start_algorithm(): save a7 Debug: 3163 16815 riscv.c:3522 riscv_get_register(): [esp32c3] a7: 0 (cached) Debug: 3164 16818 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1) Debug: 3165 16822 esp_riscv.c:316 esp_riscv_start_algorithm(): save s2 Debug: 3166 16825 riscv.c:3522 riscv_get_register(): [esp32c3] s2: 0 (cached) Debug: 3167 16830 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s2 (valid=1) Debug: 3168 16835 esp_riscv.c:316 esp_riscv_start_algorithm(): save s3 Debug: 3169 16840 riscv.c:3522 riscv_get_register(): [esp32c3] s3: 0 (cached) Debug: 3170 16843 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1) Debug: 3171 16847 esp_riscv.c:316 esp_riscv_start_algorithm(): save s4 Debug: 3172 16850 riscv.c:3522 riscv_get_register(): [esp32c3] s4: 0 (cached) Debug: 3173 16855 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1) Debug: 3174 16859 esp_riscv.c:316 esp_riscv_start_algorithm(): save s5 Debug: 3175 16863 riscv.c:3522 riscv_get_register(): [esp32c3] s5: 0 (cached) Debug: 3176 16868 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1) Debug: 3177 16873 esp_riscv.c:316 esp_riscv_start_algorithm(): save s6 Debug: 3178 16876 riscv.c:3522 riscv_get_register(): [esp32c3] s6: 0 (cached) Debug: 3179 16880 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1) Debug: 3180 16883 esp_riscv.c:316 esp_riscv_start_algorithm(): save s7 Debug: 3181 16888 riscv.c:3522 riscv_get_register(): [esp32c3] s7: 0 (cached) Debug: 3182 16891 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1) Debug: 3183 16895 esp_riscv.c:316 esp_riscv_start_algorithm(): save s8 Debug: 3184 16899 riscv.c:3522 riscv_get_register(): [esp32c3] s8: 0 (cached) Debug: 3185 16904 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1) Debug: 3186 16908 esp_riscv.c:316 esp_riscv_start_algorithm(): save s9 Debug: 3187 16912 riscv.c:3522 riscv_get_register(): [esp32c3] s9: 0 (cached) Debug: 3188 16915 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1) Debug: 3189 16921 esp_riscv.c:316 esp_riscv_start_algorithm(): save s10 Debug: 3190 16925 riscv.c:3522 riscv_get_register(): [esp32c3] s10: 0 (cached) Debug: 3191 16930 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1) Debug: 3192 16934 esp_riscv.c:316 esp_riscv_start_algorithm(): save s11 Debug: 3193 16937 riscv.c:3522 riscv_get_register(): [esp32c3] s11: 0 (cached) Debug: 3194 16941 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1) Debug: 3195 16945 esp_riscv.c:316 esp_riscv_start_algorithm(): save t3 Debug: 3196 16949 riscv.c:3522 riscv_get_register(): [esp32c3] t3: 0 (cached) Debug: 3197 16953 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1) Debug: 3198 16956 esp_riscv.c:316 esp_riscv_start_algorithm(): save t4 Debug: 3199 16960 riscv.c:3522 riscv_get_register(): [esp32c3] t4: 0 (cached) Debug: 3200 16965 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1) Debug: 3201 16968 esp_riscv.c:316 esp_riscv_start_algorithm(): save t5 Debug: 3202 16971 riscv.c:3522 riscv_get_register(): [esp32c3] t5: 0 (cached) Debug: 3203 16975 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1) Debug: 3204 16979 esp_riscv.c:316 esp_riscv_start_algorithm(): save t6 Debug: 3205 16983 riscv.c:3522 riscv_get_register(): [esp32c3] t6: 0 (cached) Debug: 3206 16986 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1) Debug: 3207 16990 esp_riscv.c:316 esp_riscv_start_algorithm(): save pc Debug: 3208 16994 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc Debug: 3209 16998 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3210 17006 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40000000 Debug: 3211 17012 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40000000 Debug: 3212 17016 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40000000 Debug: 3213 17020 riscv.c:3893 register_get(): [esp32c3] read 0x40000000 from pc (valid=0) Debug: 3214 17023 esp_riscv.c:316 esp_riscv_start_algorithm(): save mstatus Debug: 3215 17027 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mstatus Debug: 3216 17032 riscv-013.c:800 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 3217 17040 riscv-013.c:1504 register_read_direct(): {0} mstatus = 0x201800 Debug: 3218 17045 riscv.c:3539 riscv_get_register(): [esp32c3] mstatus: 201800 Debug: 3219 17048 riscv.c:3893 register_get(): [esp32c3] read 0x00201800 from mstatus (valid=1) Debug: 3220 17053 esp_riscv.c:316 esp_riscv_start_algorithm(): save misa Debug: 3221 17056 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register misa Debug: 3222 17062 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 3223 17070 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104 Debug: 3224 17074 riscv.c:3539 riscv_get_register(): [esp32c3] misa: 40101104 Debug: 3225 17080 riscv.c:3893 register_get(): [esp32c3] read 0x40101104 from misa (valid=1) Debug: 3226 17085 esp_riscv.c:316 esp_riscv_start_algorithm(): save mtvec Debug: 3227 17089 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr773 Debug: 3228 17095 riscv-013.c:800 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 3229 17106 riscv-013.c:1504 register_read_direct(): {0} csr773 = 0x1 Debug: 3230 17111 riscv.c:3539 riscv_get_register(): [esp32c3] csr773: 1 Debug: 3231 17114 riscv.c:3893 register_get(): [esp32c3] read 0x00000001 from mtvec (valid=0) Debug: 3232 17118 esp_riscv.c:316 esp_riscv_start_algorithm(): save mscratch Debug: 3233 17121 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr832 Debug: 3234 17126 riscv-013.c:800 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 3235 17135 riscv-013.c:1504 register_read_direct(): {0} csr832 = 0x0 Debug: 3236 17140 riscv.c:3539 riscv_get_register(): [esp32c3] csr832: 0 Debug: 3237 17145 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mscratch (valid=0) Debug: 3238 17149 esp_riscv.c:316 esp_riscv_start_algorithm(): save mepc Debug: 3239 17152 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mepc Debug: 3240 17158 riscv-013.c:800 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 3241 17167 riscv-013.c:1504 register_read_direct(): {0} mepc = 0x0 Debug: 3242 17172 riscv.c:3539 riscv_get_register(): [esp32c3] mepc: 0 Debug: 3243 17175 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mepc (valid=1) Debug: 3244 17179 esp_riscv.c:316 esp_riscv_start_algorithm(): save mcause Debug: 3245 17183 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mcause Debug: 3246 17187 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 3247 17195 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x0 Debug: 3248 17200 riscv.c:3539 riscv_get_register(): [esp32c3] mcause: 0 Debug: 3249 17203 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mcause (valid=1) Debug: 3250 17207 esp_riscv.c:316 esp_riscv_start_algorithm(): save mtval Debug: 3251 17211 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr835 Debug: 3252 17216 riscv-013.c:800 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 3253 17224 riscv-013.c:1504 register_read_direct(): {0} csr835 = 0x0 Debug: 3254 17227 riscv.c:3539 riscv_get_register(): [esp32c3] csr835: 0 Debug: 3255 17231 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from mtval (valid=0) Debug: 3256 17235 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg0 Debug: 3257 17239 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr928 Debug: 3258 17243 riscv-013.c:800 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 3259 17254 riscv-013.c:1504 register_read_direct(): {0} csr928 = 0x0 Debug: 3260 17258 riscv.c:3539 riscv_get_register(): [esp32c3] csr928: 0 Debug: 3261 17262 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg0 (valid=0) Debug: 3262 17268 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg1 Debug: 3263 17271 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr929 Debug: 3264 17275 riscv-013.c:800 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 3265 17285 riscv-013.c:1504 register_read_direct(): {0} csr929 = 0x0 Debug: 3266 17288 riscv.c:3539 riscv_get_register(): [esp32c3] csr929: 0 Debug: 3267 17291 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg1 (valid=0) Debug: 3268 17297 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg2 Debug: 3269 17300 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr930 Debug: 3270 17304 riscv-013.c:800 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 3271 17313 riscv-013.c:1504 register_read_direct(): {0} csr930 = 0x0 Debug: 3272 17317 riscv.c:3539 riscv_get_register(): [esp32c3] csr930: 0 Debug: 3273 17320 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg2 (valid=0) Debug: 3274 17324 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpcfg3 Debug: 3275 17329 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr931 Debug: 3276 17335 riscv-013.c:800 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 Debug: 3277 17346 riscv-013.c:1504 register_read_direct(): {0} csr931 = 0x0 Debug: 3278 17351 riscv.c:3539 riscv_get_register(): [esp32c3] csr931: 0 Debug: 3279 17355 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpcfg3 (valid=0) Debug: 3280 17362 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr0 Debug: 3281 17366 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr944 Debug: 3282 17371 riscv-013.c:800 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 3283 17382 riscv-013.c:1504 register_read_direct(): {0} csr944 = 0x0 Debug: 3284 17387 riscv.c:3539 riscv_get_register(): [esp32c3] csr944: 0 Debug: 3285 17392 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr0 (valid=0) Debug: 3286 17397 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr1 Debug: 3287 17401 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr945 Debug: 3288 17408 riscv-013.c:800 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 3289 17417 riscv-013.c:1504 register_read_direct(): {0} csr945 = 0x0 Debug: 3290 17423 riscv.c:3539 riscv_get_register(): [esp32c3] csr945: 0 Debug: 3291 17426 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr1 (valid=0) Debug: 3292 17431 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr2 Debug: 3293 17435 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr946 Debug: 3294 17442 riscv-013.c:800 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 3295 17450 riscv-013.c:1504 register_read_direct(): {0} csr946 = 0x0 Debug: 3296 17455 riscv.c:3539 riscv_get_register(): [esp32c3] csr946: 0 Debug: 3297 17459 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr2 (valid=0) Debug: 3298 17464 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr3 Debug: 3299 17467 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr947 Debug: 3300 17473 riscv-013.c:800 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 3301 17483 riscv-013.c:1504 register_read_direct(): {0} csr947 = 0x0 Debug: 3302 17488 riscv.c:3539 riscv_get_register(): [esp32c3] csr947: 0 Debug: 3303 17491 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr3 (valid=0) Debug: 3304 17496 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr4 Debug: 3305 17501 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr948 Debug: 3306 17505 riscv-013.c:800 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 3307 17514 riscv-013.c:1504 register_read_direct(): {0} csr948 = 0x0 Debug: 3308 17519 riscv.c:3539 riscv_get_register(): [esp32c3] csr948: 0 Debug: 3309 17522 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr4 (valid=0) Debug: 3310 17526 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr5 Debug: 3311 17530 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr949 Debug: 3312 17537 riscv-013.c:800 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 3313 17546 riscv-013.c:1504 register_read_direct(): {0} csr949 = 0x0 Debug: 3314 17550 riscv.c:3539 riscv_get_register(): [esp32c3] csr949: 0 Debug: 3315 17553 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr5 (valid=0) Debug: 3316 17557 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr6 Debug: 3317 17562 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr950 Debug: 3318 17567 riscv-013.c:800 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 3319 17578 riscv-013.c:1504 register_read_direct(): {0} csr950 = 0x0 Debug: 3320 17582 riscv.c:3539 riscv_get_register(): [esp32c3] csr950: 0 Debug: 3321 17585 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr6 (valid=0) Debug: 3322 17589 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr7 Debug: 3323 17592 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr951 Debug: 3324 17598 riscv-013.c:800 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 3325 17605 riscv-013.c:1504 register_read_direct(): {0} csr951 = 0x0 Debug: 3326 17610 riscv.c:3539 riscv_get_register(): [esp32c3] csr951: 0 Debug: 3327 17615 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr7 (valid=0) Debug: 3328 17619 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr8 Debug: 3329 17623 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr952 Debug: 3330 17629 riscv-013.c:800 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 3331 17639 riscv-013.c:1504 register_read_direct(): {0} csr952 = 0x0 Debug: 3332 17645 riscv.c:3539 riscv_get_register(): [esp32c3] csr952: 0 Debug: 3333 17649 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr8 (valid=0) Debug: 3334 17653 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr9 Debug: 3335 17656 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr953 Debug: 3336 17661 riscv-013.c:800 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 3337 17669 riscv-013.c:1504 register_read_direct(): {0} csr953 = 0x0 Debug: 3338 17672 riscv.c:3539 riscv_get_register(): [esp32c3] csr953: 0 Debug: 3339 17677 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr9 (valid=0) Debug: 3340 17681 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr10 Debug: 3341 17685 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr954 Debug: 3342 17689 riscv-013.c:800 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 3343 17698 riscv-013.c:1504 register_read_direct(): {0} csr954 = 0x0 Debug: 3344 17703 riscv.c:3539 riscv_get_register(): [esp32c3] csr954: 0 Debug: 3345 17707 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr10 (valid=0) Debug: 3346 17712 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr11 Debug: 3347 17716 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr955 Debug: 3348 17720 riscv-013.c:800 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 3349 17729 riscv-013.c:1504 register_read_direct(): {0} csr955 = 0x0 Debug: 3350 17732 riscv.c:3539 riscv_get_register(): [esp32c3] csr955: 0 Debug: 3351 17735 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr11 (valid=0) Debug: 3352 17741 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr12 Debug: 3353 17745 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr956 Debug: 3354 17750 riscv-013.c:800 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc Debug: 3355 17760 riscv-013.c:1504 register_read_direct(): {0} csr956 = 0x0 Debug: 3356 17764 riscv.c:3539 riscv_get_register(): [esp32c3] csr956: 0 Debug: 3357 17767 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr12 (valid=0) Debug: 3358 17772 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr13 Debug: 3359 17776 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr957 Debug: 3360 17780 riscv-013.c:800 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 3361 17788 riscv-013.c:1504 register_read_direct(): {0} csr957 = 0x0 Debug: 3362 17791 riscv.c:3539 riscv_get_register(): [esp32c3] csr957: 0 Debug: 3363 17795 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr13 (valid=0) Debug: 3364 17801 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr14 Debug: 3365 17805 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr958 Debug: 3366 17809 riscv-013.c:800 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 3367 17818 riscv-013.c:1504 register_read_direct(): {0} csr958 = 0x0 Debug: 3368 17823 riscv.c:3539 riscv_get_register(): [esp32c3] csr958: 0 Debug: 3369 17827 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr14 (valid=0) Debug: 3370 17833 esp_riscv.c:316 esp_riscv_start_algorithm(): save pmpaddr15 Debug: 3371 17837 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr959 Debug: 3372 17840 riscv-013.c:800 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 3373 17849 riscv-013.c:1504 register_read_direct(): {0} csr959 = 0x0 Debug: 3374 17854 riscv.c:3539 riscv_get_register(): [esp32c3] csr959: 0 Debug: 3375 17858 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from pmpaddr15 (valid=0) Debug: 3376 17865 esp_riscv.c:316 esp_riscv_start_algorithm(): save tselect Debug: 3377 17868 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect Debug: 3378 17872 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 3379 17882 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0 Debug: 3380 17885 riscv.c:3539 riscv_get_register(): [esp32c3] tselect: 0 Debug: 3381 17888 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tselect (valid=0) Debug: 3382 17892 esp_riscv.c:316 esp_riscv_start_algorithm(): save tdata1 Debug: 3383 17897 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1 Debug: 3384 17901 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 3385 17910 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000 Debug: 3386 17916 riscv.c:3539 riscv_get_register(): [esp32c3] tdata1: 23e00000 Debug: 3387 17920 riscv.c:3893 register_get(): [esp32c3] read 0x23e00000 from tdata1 (valid=0) Debug: 3388 17925 esp_riscv.c:316 esp_riscv_start_algorithm(): save tdata2 Debug: 3389 17931 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata2 Debug: 3390 17936 riscv-013.c:800 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 3391 17948 riscv-013.c:1504 register_read_direct(): {0} tdata2 = 0x0 Debug: 3392 17953 riscv.c:3539 riscv_get_register(): [esp32c3] tdata2: 0 Debug: 3393 17957 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tdata2 (valid=0) Debug: 3394 17963 esp_riscv.c:316 esp_riscv_start_algorithm(): save tcontrol Debug: 3395 17967 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1957 Debug: 3396 17972 riscv-013.c:800 execute_abstract_command(): command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5 Debug: 3397 17982 riscv-013.c:1504 register_read_direct(): {0} csr1957 = 0x0 Debug: 3398 17986 riscv.c:3539 riscv_get_register(): [esp32c3] csr1957: 0 Debug: 3399 17990 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from tcontrol (valid=0) Debug: 3400 17994 esp_riscv.c:316 esp_riscv_start_algorithm(): save dcsr Debug: 3401 17998 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dcsr Debug: 3402 18001 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 3403 18012 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 3404 18017 riscv.c:3539 riscv_get_register(): [esp32c3] dcsr: 4000b0c3 Debug: 3405 18020 riscv.c:3893 register_get(): [esp32c3] read 0x4000b0c3 from dcsr (valid=1) Debug: 3406 18026 esp_riscv.c:316 esp_riscv_start_algorithm(): save dpc Debug: 3407 18029 riscv.c:3522 riscv_get_register(): [esp32c3] dpc: 40000000 (cached) Debug: 3408 18032 riscv.c:3893 register_get(): [esp32c3] read 0x40000000 from dpc (valid=1) Debug: 3409 18037 esp_riscv.c:316 esp_riscv_start_algorithm(): save dscratch0 Debug: 3410 18041 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dscratch0 Debug: 3411 18045 riscv-013.c:800 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 3412 18055 riscv-013.c:1504 register_read_direct(): {0} dscratch0 = 0x0 Debug: 3413 18059 riscv.c:3539 riscv_get_register(): [esp32c3] dscratch0: 0 Debug: 3414 18063 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from dscratch0 (valid=1) Debug: 3415 18067 esp_riscv.c:316 esp_riscv_start_algorithm(): save dscratch1 Debug: 3416 18071 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1971 Debug: 3417 18075 riscv-013.c:800 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 3418 18085 riscv-013.c:1504 register_read_direct(): {0} csr1971 = 0x0 Debug: 3419 18088 riscv.c:3539 riscv_get_register(): [esp32c3] csr1971: 0 Debug: 3420 18091 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from dscratch1 (valid=0) Debug: 3421 18096 esp_riscv.c:316 esp_riscv_start_algorithm(): save hpmcounter16 Debug: 3422 18101 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr3088 Debug: 3423 18105 riscv-013.c:800 execute_abstract_command(): command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10 Debug: 3424 18114 riscv-013.c:1504 register_read_direct(): {0} csr3088 = 0x3 Debug: 3425 18119 riscv.c:3539 riscv_get_register(): [esp32c3] csr3088: 3 Debug: 3426 18123 riscv.c:3893 register_get(): [esp32c3] read 0x00000003 from hpmcounter16 (valid=0) Debug: 3427 18129 esp_riscv.c:316 esp_riscv_start_algorithm(): save priv Debug: 3428 18133 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register priv Debug: 3429 18137 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 3430 18145 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 3431 18150 riscv.c:3539 riscv_get_register(): [esp32c3] priv: 3 Debug: 3432 18154 riscv.c:3893 register_get(): [esp32c3] read 0x03 from priv (valid=0) Debug: 3433 18159 esp_riscv.c:345 esp_riscv_start_algorithm(): set sp Debug: 3434 18163 riscv.c:3906 register_set(): [esp32c3] write 0x3fc84810 to sp (valid=1) Debug: 3435 18167 riscv.c:3482 riscv_set_register(): [esp32c3] sp <- 3fc84810 Debug: 3436 18170 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc84810 to register sp Debug: 3437 18174 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fc84810 Debug: 3438 18180 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 3439 18188 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x3fc84810 to sp valid=1 Debug: 3440 18192 esp_riscv.c:345 esp_riscv_start_algorithm(): set a7 Debug: 3441 18196 riscv.c:3906 register_set(): [esp32c3] write 0x403816e4 to a7 (valid=1) Debug: 3442 18200 riscv.c:3482 riscv_set_register(): [esp32c3] a7 <- 403816e4 Debug: 3443 18204 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x403816e4 to register a7 Debug: 3444 18208 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x403816e4 Debug: 3445 18214 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 3446 18224 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x403816e4 to a7 valid=1 Debug: 3447 18231 esp_riscv.c:345 esp_riscv_start_algorithm(): set a0 Debug: 3448 18234 riscv.c:3906 register_set(): [esp32c3] write 0x00000004 to a0 (valid=1) Debug: 3449 18238 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 4 Debug: 3450 18241 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a0 Debug: 3451 18248 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x4 Debug: 3452 18253 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 3453 18263 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4 to a0 valid=1 Debug: 3454 18266 riscv.c:3294 riscv_interrupts_disable(): Disabling Interrupts Debug: 3455 18270 riscv.c:3522 riscv_get_register(): [esp32c3] mstatus: 201800 (cached) Debug: 3456 18275 riscv.c:3893 register_get(): [esp32c3] read 0x00201800 from mstatus (valid=1) Debug: 3457 18281 riscv.c:3906 register_set(): [esp32c3] write 0x00201800 to mstatus (valid=1) Debug: 3458 18286 riscv.c:3482 riscv_set_register(): [esp32c3] mstatus <- 201800 Debug: 3459 18292 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x201800 to register mstatus Debug: 3460 18297 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x201800 Debug: 3461 18301 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 3462 18312 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x201800 to mstatus valid=0 Debug: 3463 18316 esp_riscv.c:382 esp_riscv_start_algorithm(): resume at 0x40381d0c Debug: 3464 18320 riscv.c:1472 riscv_resume(): handle_breakpoints=0 Debug: 3465 18324 riscv.c:1399 resume_prep(): [0] Debug: 3466 18326 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 40381d0c Debug: 3467 18329 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40381d0c to register pc Debug: 3468 18333 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40381d0c Debug: 3469 18339 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40381d0c Debug: 3470 18344 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 3471 18353 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3472 18364 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381d0c Debug: 3473 18368 riscv-013.c:4124 riscv013_set_register(): [0] actual DPC written: 0x0000000040381d0c Debug: 3474 18373 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40381d0c to pc valid=0 Debug: 3475 18377 riscv.c:1289 riscv_resume_prep_all_harts(): [esp32c3] prep hart Debug: 3476 18383 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 3477 18388 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100f @0 Debug: 3478 18392 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 3479 18396 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0xf @1 Debug: 3480 18401 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 3481 18404 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 3482 18408 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 3483 18417 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 3484 18426 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 3485 18432 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3 Debug: 3486 18436 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr Debug: 3487 18440 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 3488 18444 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 3489 18453 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0 Debug: 3490 18459 riscv.c:1300 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped Debug: 3491 18465 riscv.c:1424 resume_prep(): [0] mark as prepped Debug: 3492 18468 riscv.c:3277 riscv_resume_go_all_harts(): [esp32c3] resuming hart Debug: 3493 18472 riscv-013.c:4190 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 3494 18476 riscv-013.c:4815 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0) Debug: 3495 18484 riscv.c:3400 riscv_invalidate_register_cache(): [0] Debug: 3496 18488 target.c:1857 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c3 Debug: 3497 18497 esp32c3.c:115 esp32c3_handle_target_event(): 18 Debug: 3498 18500 esp_riscv.c:276 esp_riscv_handle_target_event(): 18 Debug: 3499 18502 esp_algorithm.c:220 algorithm_run(): Wait algorithm completion Debug: 3500 18506 riscv.c:2078 riscv_poll_hart(): triggered a halt Debug: 3501 18512 riscv.c:2258 riscv_openocd_poll(): hart 0 halted Debug: 3502 18515 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 3503 18523 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043 Debug: 3504 18528 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x1 Debug: 3505 18532 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=1 Debug: 3506 18536 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc Debug: 3507 18540 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3508 18551 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381d0e Debug: 3509 18555 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381d0e Debug: 3510 18560 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40381d0e Debug: 3511 18565 esp_riscv.c:524 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40381d0a Debug: 3512 18577 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus. Debug: 3513 18583 esp_riscv.c:524 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40381d0e Debug: 3514 18595 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus. Debug: 3515 18600 esp_riscv.c:524 esp_riscv_read_memory(): Use 32-bit access: size: 2 count:2 start address: 0x40381d12 Debug: 3516 18610 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus. Debug: 3517 18615 riscv_semihosting.c:109 riscv_semihosting(): check 9882bd19 08339002 78b341e8 from 0x40381d0e-4 Debug: 3518 18619 riscv_semihosting.c:113 riscv_semihosting(): -> NONE (no magic) Debug: 3519 18625 target.c:1857 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 3520 18631 esp32c3.c:115 esp32c3_handle_target_event(): 0 Debug: 3521 18635 esp_riscv.c:276 esp_riscv_handle_target_event(): 0 Debug: 3522 18640 target.c:1857 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 3523 18645 target.c:5148 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable

Debug: 3524 18651 command.c:166 script_debug(): command - command mode Debug: 3525 18657 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1 Debug: 3526 18663 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 3527 18671 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3528 18678 command.c:166 script_debug(): command - mww 0x6001F048 0 Debug: 3529 18683 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 3530 18689 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3531 18696 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1 Debug: 3532 18703 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 3533 18711 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3534 18717 command.c:166 script_debug(): command - mww 0x60020048 0 Debug: 3535 18722 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 3536 18730 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3537 18735 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1 Debug: 3538 18740 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 3539 18749 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3540 18753 command.c:166 script_debug(): command - mww 0x60008090 0 Debug: 3541 18758 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 3542 18767 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3543 18771 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A Debug: 3544 18778 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 3545 18785 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3546 18789 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000 Debug: 3547 18796 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 3548 18803 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus. Debug: 3549 18808 esp32c3.c:115 esp32c3_handle_target_event(): 1 Debug: 3550 18813 esp_riscv.c:276 esp_riscv_handle_target_event(): 1 Debug: 3551 18816 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc Debug: 3552 18820 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3553 18829 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381d0e Debug: 3554 18834 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381d0e Debug: 3555 18839 riscv.c:3539 riscv_get_register(): [esp32c3] pc: 40381d0e Debug: 3556 18845 riscv.c:3893 register_get(): [esp32c3] read 0x40381d0e from pc (valid=0) Debug: 3557 18849 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0 Debug: 3558 18853 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 3559 18862 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x0 Debug: 3560 18865 riscv.c:3539 riscv_get_register(): [esp32c3] a0: 0 Debug: 3561 18868 riscv.c:3893 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1) Debug: 3562 18871 esp_riscv.c:460 esp_riscv_wait_algorithm(): Read mem params Debug: 3563 18877 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore ra Debug: 3564 18880 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to ra (valid=0) Debug: 3565 18884 riscv.c:3482 riscv_set_register(): [esp32c3] ra <- 0 Debug: 3566 18887 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register ra Debug: 3567 18893 riscv-013.c:1315 register_write_direct(): {0} ra <- 0x0 Debug: 3568 18898 riscv-013.c:800 execute_abstract_command(): command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001 Debug: 3569 18908 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to ra valid=1 Debug: 3570 18912 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore sp Debug: 3571 18915 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to sp (valid=0) Debug: 3572 18918 riscv.c:3482 riscv_set_register(): [esp32c3] sp <- 0 Debug: 3573 18923 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register sp Debug: 3574 18926 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x0 Debug: 3575 18931 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 3576 18939 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to sp valid=1 Debug: 3577 18944 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore gp Debug: 3578 18948 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to gp (valid=0) Debug: 3579 18953 riscv.c:3482 riscv_set_register(): [esp32c3] gp <- 0 Debug: 3580 18956 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register gp Debug: 3581 18960 riscv-013.c:1315 register_write_direct(): {0} gp <- 0x0 Debug: 3582 18966 riscv-013.c:800 execute_abstract_command(): command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003 Debug: 3583 18975 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to gp valid=1 Debug: 3584 18980 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tp Debug: 3585 18984 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tp (valid=0) Debug: 3586 18988 riscv.c:3482 riscv_set_register(): [esp32c3] tp <- 0 Debug: 3587 18991 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tp Debug: 3588 18995 riscv-013.c:1315 register_write_direct(): {0} tp <- 0x0 Debug: 3589 19000 riscv-013.c:800 execute_abstract_command(): command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004 Debug: 3590 19009 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tp valid=1 Debug: 3591 19016 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t0 Debug: 3592 19020 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t0 (valid=0) Debug: 3593 19025 riscv.c:3482 riscv_set_register(): [esp32c3] t0 <- 0 Debug: 3594 19030 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t0 Debug: 3595 19034 riscv-013.c:1315 register_write_direct(): {0} t0 <- 0x0 Debug: 3596 19038 riscv-013.c:800 execute_abstract_command(): command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005 Debug: 3597 19047 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t0 valid=1 Debug: 3598 19052 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t1 Debug: 3599 19056 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t1 (valid=0) Debug: 3600 19062 riscv.c:3482 riscv_set_register(): [esp32c3] t1 <- 0 Debug: 3601 19066 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t1 Debug: 3602 19071 riscv-013.c:1315 register_write_direct(): {0} t1 <- 0x0 Debug: 3603 19078 riscv-013.c:800 execute_abstract_command(): command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006 Debug: 3604 19085 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t1 valid=1 Debug: 3605 19089 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t2 Debug: 3606 19093 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t2 (valid=0) Debug: 3607 19098 riscv.c:3482 riscv_set_register(): [esp32c3] t2 <- 0 Debug: 3608 19101 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t2 Debug: 3609 19104 riscv-013.c:1315 register_write_direct(): {0} t2 <- 0x0 Debug: 3610 19109 riscv-013.c:800 execute_abstract_command(): command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007 Debug: 3611 19118 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t2 valid=1 Debug: 3612 19123 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore fp Debug: 3613 19128 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to fp (valid=0) Debug: 3614 19133 riscv.c:3482 riscv_set_register(): [esp32c3] s0 <- 0 Debug: 3615 19136 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s0 Debug: 3616 19141 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0 Debug: 3617 19145 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 3618 19154 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to fp valid=1 Debug: 3619 19157 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s1 Debug: 3620 19161 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s1 (valid=0) Debug: 3621 19165 riscv.c:3482 riscv_set_register(): [esp32c3] s1 <- 0 Debug: 3622 19167 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s1 Debug: 3623 19173 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x0 Debug: 3624 19177 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 3625 19184 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s1 valid=1 Debug: 3626 19189 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a0 Debug: 3627 19194 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a0 (valid=1) Debug: 3628 19198 riscv.c:3482 riscv_set_register(): [esp32c3] a0 <- 0 Debug: 3629 19203 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a0 Debug: 3630 19207 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x0 Debug: 3631 19212 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 3632 19220 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a0 valid=1 Debug: 3633 19224 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a1 Debug: 3634 19228 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a1 (valid=0) Debug: 3635 19233 riscv.c:3482 riscv_set_register(): [esp32c3] a1 <- 0 Debug: 3636 19236 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a1 Debug: 3637 19240 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0x0 Debug: 3638 19244 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 3639 19253 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a1 valid=1 Debug: 3640 19258 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a2 Debug: 3641 19263 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a2 (valid=0) Debug: 3642 19268 riscv.c:3482 riscv_set_register(): [esp32c3] a2 <- 0 Debug: 3643 19272 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a2 Debug: 3644 19279 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x0 Debug: 3645 19283 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 3646 19294 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a2 valid=1 Debug: 3647 19297 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a3 Debug: 3648 19301 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a3 (valid=0) Debug: 3649 19304 riscv.c:3482 riscv_set_register(): [esp32c3] a3 <- 0 Debug: 3650 19307 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a3 Debug: 3651 19314 riscv-013.c:1315 register_write_direct(): {0} a3 <- 0x0 Debug: 3652 19319 riscv-013.c:800 execute_abstract_command(): command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d Debug: 3653 19330 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a3 valid=1 Debug: 3654 19335 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a4 Debug: 3655 19339 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a4 (valid=0) Debug: 3656 19346 riscv.c:3482 riscv_set_register(): [esp32c3] a4 <- 0 Debug: 3657 19349 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a4 Debug: 3658 19353 riscv-013.c:1315 register_write_direct(): {0} a4 <- 0x0 Debug: 3659 19357 riscv-013.c:800 execute_abstract_command(): command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e Debug: 3660 19365 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a4 valid=1 Debug: 3661 19370 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a5 Debug: 3662 19375 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a5 (valid=0) Debug: 3663 19379 riscv.c:3482 riscv_set_register(): [esp32c3] a5 <- 0 Debug: 3664 19382 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a5 Debug: 3665 19387 riscv-013.c:1315 register_write_direct(): {0} a5 <- 0x0 Debug: 3666 19391 riscv-013.c:800 execute_abstract_command(): command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f Debug: 3667 19401 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a5 valid=1 Debug: 3668 19407 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a6 Debug: 3669 19411 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a6 (valid=0) Debug: 3670 19416 riscv.c:3482 riscv_set_register(): [esp32c3] a6 <- 0 Debug: 3671 19421 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a6 Debug: 3672 19424 riscv-013.c:1315 register_write_direct(): {0} a6 <- 0x0 Debug: 3673 19429 riscv-013.c:800 execute_abstract_command(): command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010 Debug: 3674 19439 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a6 valid=1 Debug: 3675 19443 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore a7 Debug: 3676 19447 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to a7 (valid=0) Debug: 3677 19451 riscv.c:3482 riscv_set_register(): [esp32c3] a7 <- 0 Debug: 3678 19454 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a7 Debug: 3679 19458 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x0 Debug: 3680 19463 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 3681 19471 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to a7 valid=1 Debug: 3682 19476 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s2 Debug: 3683 19479 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s2 (valid=0) Debug: 3684 19485 riscv.c:3482 riscv_set_register(): [esp32c3] s2 <- 0 Debug: 3685 19488 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s2 Debug: 3686 19492 riscv-013.c:1315 register_write_direct(): {0} s2 <- 0x0 Debug: 3687 19497 riscv-013.c:800 execute_abstract_command(): command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012 Debug: 3688 19505 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s2 valid=1 Debug: 3689 19509 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s3 Debug: 3690 19513 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s3 (valid=0) Debug: 3691 19517 riscv.c:3482 riscv_set_register(): [esp32c3] s3 <- 0 Debug: 3692 19520 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s3 Debug: 3693 19524 riscv-013.c:1315 register_write_direct(): {0} s3 <- 0x0 Debug: 3694 19529 riscv-013.c:800 execute_abstract_command(): command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013 Debug: 3695 19538 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s3 valid=1 Debug: 3696 19542 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s4 Debug: 3697 19548 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s4 (valid=0) Debug: 3698 19552 riscv.c:3482 riscv_set_register(): [esp32c3] s4 <- 0 Debug: 3699 19555 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s4 Debug: 3700 19558 riscv-013.c:1315 register_write_direct(): {0} s4 <- 0x0 Debug: 3701 19564 riscv-013.c:800 execute_abstract_command(): command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014 Debug: 3702 19574 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s4 valid=1 Debug: 3703 19579 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s5 Debug: 3704 19583 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s5 (valid=0) Debug: 3705 19587 riscv.c:3482 riscv_set_register(): [esp32c3] s5 <- 0 Debug: 3706 19592 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s5 Debug: 3707 19596 riscv-013.c:1315 register_write_direct(): {0} s5 <- 0x0 Debug: 3708 19600 riscv-013.c:800 execute_abstract_command(): command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015 Debug: 3709 19609 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s5 valid=1 Debug: 3710 19614 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s6 Debug: 3711 19617 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s6 (valid=0) Debug: 3712 19623 riscv.c:3482 riscv_set_register(): [esp32c3] s6 <- 0 Debug: 3713 19626 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s6 Debug: 3714 19630 riscv-013.c:1315 register_write_direct(): {0} s6 <- 0x0 Debug: 3715 19634 riscv-013.c:800 execute_abstract_command(): command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016 Debug: 3716 19644 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s6 valid=1 Debug: 3717 19648 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s7 Debug: 3718 19651 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s7 (valid=0) Debug: 3719 19655 riscv.c:3482 riscv_set_register(): [esp32c3] s7 <- 0 Debug: 3720 19658 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s7 Debug: 3721 19663 riscv-013.c:1315 register_write_direct(): {0} s7 <- 0x0 Debug: 3722 19667 riscv-013.c:800 execute_abstract_command(): command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017 Debug: 3723 19676 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s7 valid=1 Debug: 3724 19680 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s8 Debug: 3725 19685 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s8 (valid=0) Debug: 3726 19689 riscv.c:3482 riscv_set_register(): [esp32c3] s8 <- 0 Debug: 3727 19692 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s8 Debug: 3728 19697 riscv-013.c:1315 register_write_direct(): {0} s8 <- 0x0 Debug: 3729 19702 riscv-013.c:800 execute_abstract_command(): command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018 Debug: 3730 19713 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s8 valid=1 Debug: 3731 19717 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s9 Debug: 3732 19720 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s9 (valid=0) Debug: 3733 19724 riscv.c:3482 riscv_set_register(): [esp32c3] s9 <- 0 Debug: 3734 19727 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s9 Debug: 3735 19732 riscv-013.c:1315 register_write_direct(): {0} s9 <- 0x0 Debug: 3736 19737 riscv-013.c:800 execute_abstract_command(): command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019 Debug: 3737 19745 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s9 valid=1 Debug: 3738 19749 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s10 Debug: 3739 19752 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s10 (valid=0) Debug: 3740 19756 riscv.c:3482 riscv_set_register(): [esp32c3] s10 <- 0 Debug: 3741 19759 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s10 Debug: 3742 19765 riscv-013.c:1315 register_write_direct(): {0} s10 <- 0x0 Debug: 3743 19768 riscv-013.c:800 execute_abstract_command(): command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a Debug: 3744 19776 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s10 valid=1 Debug: 3745 19781 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore s11 Debug: 3746 19785 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to s11 (valid=0) Debug: 3747 19790 riscv.c:3482 riscv_set_register(): [esp32c3] s11 <- 0 Debug: 3748 19795 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s11 Debug: 3749 19799 riscv-013.c:1315 register_write_direct(): {0} s11 <- 0x0 Debug: 3750 19803 riscv-013.c:800 execute_abstract_command(): command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b Debug: 3751 19813 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to s11 valid=1 Debug: 3752 19818 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t3 Debug: 3753 19823 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t3 (valid=0) Debug: 3754 19827 riscv.c:3482 riscv_set_register(): [esp32c3] t3 <- 0 Debug: 3755 19830 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t3 Debug: 3756 19834 riscv-013.c:1315 register_write_direct(): {0} t3 <- 0x0 Debug: 3757 19838 riscv-013.c:800 execute_abstract_command(): command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c Debug: 3758 19847 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t3 valid=1 Debug: 3759 19852 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t4 Debug: 3760 19856 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t4 (valid=0) Debug: 3761 19860 riscv.c:3482 riscv_set_register(): [esp32c3] t4 <- 0 Debug: 3762 19863 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t4 Debug: 3763 19867 riscv-013.c:1315 register_write_direct(): {0} t4 <- 0x0 Debug: 3764 19872 riscv-013.c:800 execute_abstract_command(): command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d Debug: 3765 19881 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t4 valid=1 Debug: 3766 19885 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t5 Debug: 3767 19890 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t5 (valid=0) Debug: 3768 19893 riscv.c:3482 riscv_set_register(): [esp32c3] t5 <- 0 Debug: 3769 19897 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t5 Debug: 3770 19904 riscv-013.c:1315 register_write_direct(): {0} t5 <- 0x0 Debug: 3771 19908 riscv-013.c:800 execute_abstract_command(): command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e Debug: 3772 19917 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t5 valid=1 Debug: 3773 19923 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore t6 Debug: 3774 19927 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to t6 (valid=0) Debug: 3775 19932 riscv.c:3482 riscv_set_register(): [esp32c3] t6 <- 0 Debug: 3776 19937 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t6 Debug: 3777 19941 riscv-013.c:1315 register_write_direct(): {0} t6 <- 0x0 Debug: 3778 19945 riscv-013.c:800 execute_abstract_command(): command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f Debug: 3779 19955 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to t6 valid=1 Debug: 3780 19958 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pc Debug: 3781 19961 riscv.c:3906 register_set(): [esp32c3] write 0x40000000 to pc (valid=0) Debug: 3782 19967 riscv.c:3482 riscv_set_register(): [esp32c3] pc <- 40000000 Debug: 3783 19970 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40000000 to register pc Debug: 3784 19975 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40000000 Debug: 3785 19982 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40000000 Debug: 3786 19986 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 3787 19996 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 3788 20004 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40000000 Debug: 3789 20007 riscv-013.c:4124 riscv013_set_register(): [0] actual DPC written: 0x0000000040000000 Debug: 3790 20013 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40000000 to pc valid=0 Debug: 3791 20017 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mstatus Debug: 3792 20020 riscv.c:3906 register_set(): [esp32c3] write 0x00201800 to mstatus (valid=0) Debug: 3793 20024 riscv.c:3482 riscv_set_register(): [esp32c3] mstatus <- 201800 Debug: 3794 20030 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x201800 to register mstatus Debug: 3795 20034 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x201800 Debug: 3796 20038 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 3797 20049 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x201800 to mstatus valid=0 Debug: 3798 20054 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore misa Debug: 3799 20057 riscv.c:3906 register_set(): [esp32c3] write 0x40101104 to misa (valid=0) Debug: 3800 20063 riscv.c:3482 riscv_set_register(): [esp32c3] misa <- 40101104 Debug: 3801 20068 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40101104 to register misa Debug: 3802 20073 riscv-013.c:1315 register_write_direct(): {0} misa <- 0x40101104 Debug: 3803 20080 riscv-013.c:800 execute_abstract_command(): command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301 Debug: 3804 20087 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40101104 to misa valid=0 Debug: 3805 20092 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mtvec Debug: 3806 20096 riscv.c:3906 register_set(): [esp32c3] write 0x00000001 to mtvec (valid=0) Debug: 3807 20100 riscv.c:3482 riscv_set_register(): [esp32c3] csr773 <- 1 Debug: 3808 20103 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register csr773 Debug: 3809 20108 riscv-013.c:1315 register_write_direct(): {0} csr773 <- 0x1 Debug: 3810 20113 riscv-013.c:800 execute_abstract_command(): command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305 Debug: 3811 20120 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x1 to mtvec valid=0 Debug: 3812 20126 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mscratch Debug: 3813 20131 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mscratch (valid=0) Debug: 3814 20135 riscv.c:3482 riscv_set_register(): [esp32c3] csr832 <- 0 Debug: 3815 20139 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr832 Debug: 3816 20143 riscv-013.c:1315 register_write_direct(): {0} csr832 <- 0x0 Debug: 3817 20147 riscv-013.c:800 execute_abstract_command(): command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340 Debug: 3818 20155 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mscratch valid=0 Debug: 3819 20159 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mepc Debug: 3820 20162 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mepc (valid=0) Debug: 3821 20166 riscv.c:3482 riscv_set_register(): [esp32c3] mepc <- 0 Debug: 3822 20170 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register mepc Debug: 3823 20174 riscv-013.c:1315 register_write_direct(): {0} mepc <- 0x0 Debug: 3824 20179 riscv-013.c:800 execute_abstract_command(): command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341 Debug: 3825 20189 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mepc valid=0 Debug: 3826 20193 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mcause Debug: 3827 20196 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mcause (valid=0) Debug: 3828 20201 riscv.c:3482 riscv_set_register(): [esp32c3] mcause <- 0 Debug: 3829 20204 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register mcause Debug: 3830 20208 riscv-013.c:1315 register_write_direct(): {0} mcause <- 0x0 Debug: 3831 20213 riscv-013.c:800 execute_abstract_command(): command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342 Debug: 3832 20221 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mcause valid=0 Debug: 3833 20227 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore mtval Debug: 3834 20231 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to mtval (valid=0) Debug: 3835 20235 riscv.c:3482 riscv_set_register(): [esp32c3] csr835 <- 0 Debug: 3836 20239 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr835 Debug: 3837 20243 riscv-013.c:1315 register_write_direct(): {0} csr835 <- 0x0 Debug: 3838 20248 riscv-013.c:800 execute_abstract_command(): command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343 Debug: 3839 20255 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to mtval valid=0 Debug: 3840 20259 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg0 Debug: 3841 20264 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg0 (valid=0) Debug: 3842 20268 riscv.c:3482 riscv_set_register(): [esp32c3] csr928 <- 0 Debug: 3843 20271 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr928 Debug: 3844 20275 riscv-013.c:1315 register_write_direct(): {0} csr928 <- 0x0 Debug: 3845 20282 riscv-013.c:800 execute_abstract_command(): command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0 Debug: 3846 20291 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg0 valid=0 Debug: 3847 20297 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg1 Debug: 3848 20301 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg1 (valid=0) Debug: 3849 20305 riscv.c:3482 riscv_set_register(): [esp32c3] csr929 <- 0 Debug: 3850 20308 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr929 Debug: 3851 20313 riscv-013.c:1315 register_write_direct(): {0} csr929 <- 0x0 Debug: 3852 20317 riscv-013.c:800 execute_abstract_command(): command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1 Debug: 3853 20328 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg1 valid=0 Debug: 3854 20332 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg2 Debug: 3855 20336 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg2 (valid=0) Debug: 3856 20340 riscv.c:3482 riscv_set_register(): [esp32c3] csr930 <- 0 Debug: 3857 20344 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr930 Debug: 3858 20348 riscv-013.c:1315 register_write_direct(): {0} csr930 <- 0x0 Debug: 3859 20352 riscv-013.c:800 execute_abstract_command(): command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2 Debug: 3860 20362 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg2 valid=0 Debug: 3861 20366 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpcfg3 Debug: 3862 20369 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpcfg3 (valid=0) Debug: 3863 20374 riscv.c:3482 riscv_set_register(): [esp32c3] csr931 <- 0 Debug: 3864 20378 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr931 Debug: 3865 20382 riscv-013.c:1315 register_write_direct(): {0} csr931 <- 0x0 Debug: 3866 20386 riscv-013.c:800 execute_abstract_command(): command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3 Debug: 3867 20396 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpcfg3 valid=0 Debug: 3868 20400 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr0 Debug: 3869 20406 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr0 (valid=0) Debug: 3870 20410 riscv.c:3482 riscv_set_register(): [esp32c3] csr944 <- 0 Debug: 3871 20414 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr944 Debug: 3872 20420 riscv-013.c:1315 register_write_direct(): {0} csr944 <- 0x0 Debug: 3873 20424 riscv-013.c:800 execute_abstract_command(): command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0 Debug: 3874 20433 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr0 valid=0 Debug: 3875 20439 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr1 Debug: 3876 20444 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr1 (valid=0) Debug: 3877 20450 riscv.c:3482 riscv_set_register(): [esp32c3] csr945 <- 0 Debug: 3878 20454 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr945 Debug: 3879 20459 riscv-013.c:1315 register_write_direct(): {0} csr945 <- 0x0 Debug: 3880 20463 riscv-013.c:800 execute_abstract_command(): command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1 Debug: 3881 20471 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr1 valid=0 Debug: 3882 20477 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr2 Debug: 3883 20483 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr2 (valid=0) Debug: 3884 20487 riscv.c:3482 riscv_set_register(): [esp32c3] csr946 <- 0 Debug: 3885 20490 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr946 Debug: 3886 20495 riscv-013.c:1315 register_write_direct(): {0} csr946 <- 0x0 Debug: 3887 20500 riscv-013.c:800 execute_abstract_command(): command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2 Debug: 3888 20508 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr2 valid=0 Debug: 3889 20514 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr3 Debug: 3890 20517 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr3 (valid=0) Debug: 3891 20521 riscv.c:3482 riscv_set_register(): [esp32c3] csr947 <- 0 Debug: 3892 20524 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr947 Debug: 3893 20530 riscv-013.c:1315 register_write_direct(): {0} csr947 <- 0x0 Debug: 3894 20534 riscv-013.c:800 execute_abstract_command(): command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3 Debug: 3895 20542 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr3 valid=0 Debug: 3896 20547 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr4 Debug: 3897 20551 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr4 (valid=0) Debug: 3898 20555 riscv.c:3482 riscv_set_register(): [esp32c3] csr948 <- 0 Debug: 3899 20558 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr948 Debug: 3900 20563 riscv-013.c:1315 register_write_direct(): {0} csr948 <- 0x0 Debug: 3901 20567 riscv-013.c:800 execute_abstract_command(): command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4 Debug: 3902 20575 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr4 valid=0 Debug: 3903 20581 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr5 Debug: 3904 20585 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr5 (valid=0) Debug: 3905 20590 riscv.c:3482 riscv_set_register(): [esp32c3] csr949 <- 0 Debug: 3906 20595 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr949 Debug: 3907 20599 riscv-013.c:1315 register_write_direct(): {0} csr949 <- 0x0 Debug: 3908 20603 riscv-013.c:800 execute_abstract_command(): command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5 Debug: 3909 20612 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr5 valid=0 Debug: 3910 20617 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr6 Debug: 3911 20621 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr6 (valid=0) Debug: 3912 20628 riscv.c:3482 riscv_set_register(): [esp32c3] csr950 <- 0 Debug: 3913 20632 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr950 Debug: 3914 20637 riscv-013.c:1315 register_write_direct(): {0} csr950 <- 0x0 Debug: 3915 20642 riscv-013.c:800 execute_abstract_command(): command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6 Debug: 3916 20652 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr6 valid=0 Debug: 3917 20658 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr7 Debug: 3918 20661 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr7 (valid=0) Debug: 3919 20666 riscv.c:3482 riscv_set_register(): [esp32c3] csr951 <- 0 Debug: 3920 20669 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr951 Debug: 3921 20675 riscv-013.c:1315 register_write_direct(): {0} csr951 <- 0x0 Debug: 3922 20680 riscv-013.c:800 execute_abstract_command(): command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7 Debug: 3923 20690 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr7 valid=0 Debug: 3924 20695 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr8 Debug: 3925 20698 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr8 (valid=0) Debug: 3926 20702 riscv.c:3482 riscv_set_register(): [esp32c3] csr952 <- 0 Debug: 3927 20706 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr952 Debug: 3928 20711 riscv-013.c:1315 register_write_direct(): {0} csr952 <- 0x0 Debug: 3929 20716 riscv-013.c:800 execute_abstract_command(): command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8 Debug: 3930 20725 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr8 valid=0 Debug: 3931 20730 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr9 Debug: 3932 20733 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr9 (valid=0) Debug: 3933 20738 riscv.c:3482 riscv_set_register(): [esp32c3] csr953 <- 0 Debug: 3934 20741 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr953 Debug: 3935 20746 riscv-013.c:1315 register_write_direct(): {0} csr953 <- 0x0 Debug: 3936 20750 riscv-013.c:800 execute_abstract_command(): command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9 Debug: 3937 20758 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr9 valid=0 Debug: 3938 20762 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr10 Debug: 3939 20766 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr10 (valid=0) Debug: 3940 20770 riscv.c:3482 riscv_set_register(): [esp32c3] csr954 <- 0 Debug: 3941 20774 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr954 Debug: 3942 20779 riscv-013.c:1315 register_write_direct(): {0} csr954 <- 0x0 Debug: 3943 20784 riscv-013.c:800 execute_abstract_command(): command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba Debug: 3944 20792 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr10 valid=0 Debug: 3945 20798 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr11 Debug: 3946 20801 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr11 (valid=0) Debug: 3947 20805 riscv.c:3482 riscv_set_register(): [esp32c3] csr955 <- 0 Debug: 3948 20808 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr955 Debug: 3949 20813 riscv-013.c:1315 register_write_direct(): {0} csr955 <- 0x0 Debug: 3950 20818 riscv-013.c:800 execute_abstract_command(): command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb Debug: 3951 20829 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr11 valid=0 Debug: 3952 20835 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr12 Debug: 3953 20839 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr12 (valid=0) Debug: 3954 20845 riscv.c:3482 riscv_set_register(): [esp32c3] csr956 <- 0 Debug: 3955 20849 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr956 Debug: 3956 20853 riscv-013.c:1315 register_write_direct(): {0} csr956 <- 0x0 Debug: 3957 20857 riscv-013.c:800 execute_abstract_command(): command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc Debug: 3958 20867 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr12 valid=0 Debug: 3959 20872 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr13 Debug: 3960 20877 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr13 (valid=0) Debug: 3961 20881 riscv.c:3482 riscv_set_register(): [esp32c3] csr957 <- 0 Debug: 3962 20884 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr957 Debug: 3963 20888 riscv-013.c:1315 register_write_direct(): {0} csr957 <- 0x0 Debug: 3964 20893 riscv-013.c:800 execute_abstract_command(): command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd Debug: 3965 20903 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr13 valid=0 Debug: 3966 20910 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr14 Debug: 3967 20913 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr14 (valid=0) Debug: 3968 20917 riscv.c:3482 riscv_set_register(): [esp32c3] csr958 <- 0 Debug: 3969 20922 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr958 Debug: 3970 20926 riscv-013.c:1315 register_write_direct(): {0} csr958 <- 0x0 Debug: 3971 20931 riscv-013.c:800 execute_abstract_command(): command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be Debug: 3972 20940 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr14 valid=0 Debug: 3973 20945 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore pmpaddr15 Debug: 3974 20950 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to pmpaddr15 (valid=0) Debug: 3975 20955 riscv.c:3482 riscv_set_register(): [esp32c3] csr959 <- 0 Debug: 3976 20958 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr959 Debug: 3977 20963 riscv-013.c:1315 register_write_direct(): {0} csr959 <- 0x0 Debug: 3978 20967 riscv-013.c:800 execute_abstract_command(): command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf Debug: 3979 20976 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to pmpaddr15 valid=0 Debug: 3980 20980 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tselect Debug: 3981 20985 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tselect (valid=0) Debug: 3982 20989 riscv.c:3482 riscv_set_register(): [esp32c3] tselect <- 0 Debug: 3983 20992 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect Debug: 3984 20997 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0 Debug: 3985 21002 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0 Debug: 3986 21012 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0 Debug: 3987 21016 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tdata1 Debug: 3988 21019 riscv.c:3906 register_set(): [esp32c3] write 0x23e00000 to tdata1 (valid=0) Debug: 3989 21023 riscv.c:3482 riscv_set_register(): [esp32c3] tdata1 <- 23e00000 Debug: 3990 21027 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x23e00000 to register tdata1 Debug: 3991 21032 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x23e00000 Debug: 3992 21037 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1 Debug: 3993 21045 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x23e00000 to tdata1 valid=0 Debug: 3994 21051 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tdata2 Debug: 3995 21054 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tdata2 (valid=0) Debug: 3996 21058 riscv.c:3482 riscv_set_register(): [esp32c3] tdata2 <- 0 Debug: 3997 21062 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tdata2 Debug: 3998 21067 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x0 Debug: 3999 21071 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2 Debug: 4000 21080 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tdata2 valid=0 Debug: 4001 21084 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore tcontrol Debug: 4002 21087 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to tcontrol (valid=0) Debug: 4003 21091 riscv.c:3482 riscv_set_register(): [esp32c3] csr1957 <- 0 Debug: 4004 21095 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr1957 Debug: 4005 21099 riscv-013.c:1315 register_write_direct(): {0} csr1957 <- 0x0 Debug: 4006 21104 riscv-013.c:800 execute_abstract_command(): command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5 Debug: 4007 21113 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to tcontrol valid=0 Debug: 4008 21118 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dcsr Debug: 4009 21122 riscv.c:3906 register_set(): [esp32c3] write 0x4000b0c3 to dcsr (valid=0) Debug: 4010 21128 riscv.c:3482 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3 Debug: 4011 21132 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr Debug: 4012 21138 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 4013 21145 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 4014 21155 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0 Debug: 4015 21162 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dpc Debug: 4016 21166 riscv.c:3906 register_set(): [esp32c3] write 0x40000000 to dpc (valid=0) Debug: 4017 21171 riscv.c:3482 riscv_set_register(): [esp32c3] dpc <- 40000000 Debug: 4018 21177 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40000000 to register dpc Debug: 4019 21181 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40000000 Debug: 4020 21185 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 4021 21194 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x40000000 to dpc valid=1 Debug: 4022 21200 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dscratch0 Debug: 4023 21204 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to dscratch0 (valid=0) Debug: 4024 21210 riscv.c:3482 riscv_set_register(): [esp32c3] dscratch0 <- 0 Debug: 4025 21214 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register dscratch0 Debug: 4026 21218 riscv-013.c:1315 register_write_direct(): {0} dscratch0 <- 0x0 Debug: 4027 21223 riscv-013.c:800 execute_abstract_command(): command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2 Debug: 4028 21232 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch0 valid=0 Debug: 4029 21237 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore dscratch1 Debug: 4030 21240 riscv.c:3906 register_set(): [esp32c3] write 0x00000000 to dscratch1 (valid=0) Debug: 4031 21245 riscv.c:3482 riscv_set_register(): [esp32c3] csr1971 <- 0 Debug: 4032 21248 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr1971 Debug: 4033 21254 riscv-013.c:1315 register_write_direct(): {0} csr1971 <- 0x0 Debug: 4034 21260 riscv-013.c:800 execute_abstract_command(): command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3 Debug: 4035 21269 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch1 valid=0 Debug: 4036 21275 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore hpmcounter16 Debug: 4037 21280 riscv.c:3906 register_set(): [esp32c3] write 0x00000003 to hpmcounter16 (valid=0) Debug: 4038 21285 riscv.c:3482 riscv_set_register(): [esp32c3] csr3088 <- 3 Debug: 4039 21288 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register csr3088 Debug: 4040 21292 riscv-013.c:1315 register_write_direct(): {0} csr3088 <- 0x3 Debug: 4041 21296 riscv-013.c:800 execute_abstract_command(): command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10 Debug: 4042 21306 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x3 to hpmcounter16 valid=0 Debug: 4043 21311 esp_riscv.c:481 esp_riscv_wait_algorithm(): restore priv Debug: 4044 21316 riscv.c:3906 register_set(): [esp32c3] write 0x03 to priv (valid=0) Debug: 4045 21320 riscv.c:3482 riscv_set_register(): [esp32c3] priv <- 3 Debug: 4046 21323 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register priv Debug: 4047 21328 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 4048 21337 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 4049 21342 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 4050 21349 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 4051 21358 riscv.c:3501 riscv_set_register(): [esp32c3] wrote 0x3 to priv valid=0 Debug: 4052 21363 esp_algorithm.c:248 algorithm_run(): Got algorithm RC 0x0 Debug: 4053 21367 target.c:2203 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381d0c Debug: 4054 21372 target.c:1983 print_wa_layout(): 0x40380000-0x40381d0b (7436 bytes) Debug: 4055 21375 target.c:1983 print_wa_layout(): 0x40381d0c-0x40383fff (8948 bytes) Debug: 4056 21382 target.c:2203 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3fc84428 Debug: 4057 21389 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fc84427 (1064 bytes) Debug: 4058 21394 target.c:1983 print_wa_layout(): 0x3fc84428-0x3fca3fff (130008 bytes) Debug: 4059 21398 target.c:2203 target_free_working_area_restore(): freed 7436 bytes of working area at address 0x40380000 Debug: 4060 21404 target.c:1983 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes) Debug: 4061 21410 target.c:2203 target_free_working_area_restore(): freed 1064 bytes of working area at address 0x3fc84000 Debug: 4062 21415 target.c:1983 print_wa_layout(): 0x3fc84000-0x3fca3fff (131072 bytes) Error: 4063 21419 esp_flash.c:344 esp_flash_get_size(): Failed to get flash size! Debug: 4064 21422 esp_flash.c:345 esp_flash_get_size(): esp_flash_get_size size 0x0 Error: 4065 21427 esp_flash.c:980 esp_flash_probe(): Failed to probe flash, size 0 KB Error: 4066 21432 core.c:282 get_flash_bank_by_name(): auto_probe failed Error: 4067 21436 esp_flash.c:1289 esp_target_to_flash_bank(): Failed to find bank 'esp32c3.flash'! Debug: 4068 21442 command.c:556 run_command(): Command 'esp compression' failed with error code -4 User : 4069 21447 command.c:619 command_run_line(): Debug: 4070 21450 riscv.c:490 riscv_deinit_target(): riscv_deinit_target() Debug: 4071 21453 riscv-013.c:1537 deinit_target(): riscv_deinit_target() Debug: 4072 21458 target.c:2236 target_free_all_working_areas_restore(): freeing all working areas Debug: 4073 21464 target.c:1983 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes)

Modified the command slightly to get it to run openocd -d3 -f board/esp32c3-builtin.cfg -c "init;halt;flash probe 0"

I guess this is the feedback you wanted. To get this I needed to disconnect and reconnect the device. At the end I've included the log I saw before doing this in case it is a clue to what is going on.

C:\Users\brenton\Documents\HBS\hello_world>openocd -d3 -f board/esp32c3-builtin.cfg -c "init;halt;flash probe 0" Open On-Chip Debugger v0.11.0-esp32-20211220 (2021-12-20-15:43) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html User : 13 7 options.c:63 configuration_output_handler(): debug_level: 3 User : 14 11 options.c:63 configuration_output_handler(): Debug: 15 13 options.c:244 add_default_dirs(): bindir=/builds/idf/openocd-esp32/_build/../openocd-esp32/bin Debug: 16 19 options.c:245 add_default_dirs(): pkgdatadir=/builds/idf/openocd-esp32/_build/../openocd-esp32/share/openocd Debug: 17 25 options.c:246 add_default_dirs(): exepath=C:/Espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/bin Debug: 18 33 options.c:247 add_default_dirs(): bin2data=../share/openocd Debug: 19 36 configuration.c:42 add_script_search_dir(): adding C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts Debug: 20 44 configuration.c:42 add_script_search_dir(): adding C:/Users/brenton/AppData/Roaming/OpenOCD Debug: 21 50 configuration.c:42 add_script_search_dir(): adding C:/Espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/bin/../share/openocd/site Debug: 22 57 configuration.c:42 add_script_search_dir(): adding C:/Espressif/tools/openocd-esp32/v0.11.0-esp32-20211220/openocd-esp32/bin/../share/openocd/scripts Debug: 23 66 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/board/esp32c3-builtin.cfg Debug: 24 77 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/interface/esp_usb_jtag.cfg Debug: 25 85 command.c:146 script_debug(): command - adapter driver esp_usb_jtag Info : 27 89 transport.c:117 allow_transports(): only one transport option; autoselect 'jtag' Debug: 28 95 command.c:146 script_debug(): command - espusbjtag vid_pid 0x303a 0x1001 Info : 30 99 esp_usb_jtag.c:899 esp_usb_jtag_vid_pid(): esp_usb_jtag: VID set to 0x303a and PID to 0x1001 Debug: 31 104 command.c:146 script_debug(): command - espusbjtag caps_descriptor 0x2000 Info : 33 111 esp_usb_jtag.c:912 esp_usb_jtag_caps_descriptor(): esp_usb_jtag: capabilities descriptor set to 0x2000 Debug: 34 116 command.c:146 script_debug(): command - adapter speed 40000 Debug: 36 119 core.c:1822 jtag_config_khz(): handle jtag khz Debug: 37 123 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 38 128 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 39 132 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/target/esp32c3.cfg Debug: 40 141 command.c:146 script_debug(): command - transport select jtag Warn : 41 144 transport.c:286 jim_transport_select(): Transport "jtag" was already selected Debug: 42 149 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/bitsbytes.tcl Debug: 43 159 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/memory.tcl Debug: 44 167 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/mmr_helpers.tcl Debug: 45 174 configuration.c:97 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20211220\openocd-esp32\share\openocd\scripts/target/esp_common.cfg Debug: 46 184 command.c:146 script_debug(): command - add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock are optional Debug: 48 194 command.c:1115 help_add_command(): added 'program_esp' help text Debug: 49 199 command.c:146 script_debug(): command - add_usage_text program_esp [address] [verify] [reset] [exit] [compress] [restore_clock] Debug: 51 206 command.c:1141 help_add_command(): added 'program_esp' usage text Debug: 52 209 command.c:146 script_debug(): command - add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project Debug: 54 219 command.c:1115 help_add_command(): added 'program_esp_bins' help text Debug: 55 223 command.c:146 script_debug(): command - add_usage_text program_esp_bins flasher_args.json [verify] [reset] [exit] [compress] [restore_clock] Debug: 57 232 command.c:1141 help_add_command(): added 'program_esp_bins' usage text Debug: 58 236 command.c:146 script_debug(): command - add_help_text esp_get_mac Print MAC address of the chip. Use a format argument to return formatted MAC value Debug: 60 245 command.c:1115 help_add_command(): added 'esp_get_mac' help text Debug: 61 248 command.c:146 script_debug(): command - add_usage_text esp_get_mac [format] Debug: 63 254 command.c:1141 help_add_command(): added 'esp_get_mac' usage text Debug: 64 259 command.c:146 script_debug(): command - jtag newtap esp32c3 cpu -irlen 5 -expected-id 0x00005c25 Debug: 65 264 tcl.c:572 jim_newtap_cmd(): Creating New Tap, Chip: esp32c3, Tap: cpu, Dotted: esp32c3.cpu, 4 params Debug: 66 269 tcl.c:596 jim_newtap_cmd(): Processing option: -irlen Debug: 67 274 tcl.c:596 jim_newtap_cmd(): Processing option: -expected-id Debug: 68 278 core.c:1488 jtag_tap_init(): Created Tap: esp32c3.cpu @ abs position 0, irlen 5, capture: 0x1 mask: 0x3 Debug: 69 285 command.c:146 script_debug(): command - target create esp32c3 esp32c3 -chain-position esp32c3.cpu -rtos FreeRTOS Debug: 70 293 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 71 297 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 72 301 FreeRTOS.c:1242 FreeRTOS_create(): FreeRTOS_create Debug: 73 306 command.c:376 register_command(): command 'set_enable_virtual' is already registered in 'riscv' context Debug: 74 311 command.c:376 register_command(): command 'set_enable_virtual' is already registered in 'riscv' context Debug: 75 316 command.c:146 script_debug(): command - esp32c3 configure -event reset-assert-post esp32c3_soc_reset Debug: 76 323 command.c:146 script_debug(): command - esp32c3 configure -event halted esp32c3_wdt_disable

Debug: 77 329 command.c:146 script_debug(): command - esp32c3 configure -event examine-end

Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default

arm semihosting enable
arm semihosting_resexit enable

Debug: 78 345 command.c:146 script_debug(): command - esp32c3 configure -event gdb-attach

'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map

halt
if { [esp32c3_memprot_is_enabled] } {
    # 'reset halt' to disable memory protection and allow flasher to work correctly
    echo "Memory protection is enabled. Reset target to disable it..."
    reset halt
}
# by default mask interrupts while stepping
riscv maskisr steponly

Debug: 79 373 command.c:146 script_debug(): command - esp32c3 configure -work-area-phys 0x40380000 -work-area-virt 0x40380000 -work-area-size 0x4000 -work-area-backup 1 Debug: 80 382 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 81 386 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 82 390 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 83 396 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 84 401 command.c:146 script_debug(): command - esp32c3 configure -alt-work-area-phys 0x3FC84000 -alt-work-area-virt 0x3FC84000 -alt-work-area-size 0x20000 -alt-work-area-backup 1 Debug: 85 411 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 86 415 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 87 420 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 88 425 target.c:2218 target_free_all_working_areas_restore(): freeing all working areas Debug: 89 430 command.c:146 script_debug(): command - flash bank esp32c3.flash esp32c3 0x0 0 0 0 esp32c3 Debug: 91 434 command.c:376 register_command(): command 'esp' is already registered in '' context Debug: 92 441 tcl.c:1319 handle_flash_bank_command(): 'esp32c3' driver usage field missing Debug: 93 445 command.c:146 script_debug(): command - flash bank esp32c3.irom esp32c3 0x0 0 0 0 esp32c3 Debug: 95 450 command.c:376 register_command(): command 'esp' is already registered in '' context Debug: 96 456 command.c:376 register_command(): command 'appimage_offset' is already registered in 'esp' context Debug: 97 462 command.c:376 register_command(): command 'compression' is already registered in 'esp' context Debug: 98 469 command.c:376 register_command(): command 'verify_bank_hash' is already registered in 'esp' context Debug: 99 474 command.c:376 register_command(): command 'flash_stub_clock_boost' is already registered in 'esp' context Debug: 100 481 tcl.c:1319 handle_flash_bank_command(): 'esp32c3' driver usage field missing Debug: 101 486 command.c:146 script_debug(): command - flash bank esp32c3.drom esp32c3 0x0 0 0 0 esp32c3 Debug: 103 491 command.c:376 register_command(): command 'esp' is already registered in '' context Debug: 104 496 command.c:376 register_command(): command 'appimage_offset' is already registered in 'esp' context Debug: 105 502 command.c:376 register_command(): command 'compression' is already registered in 'esp' context Debug: 106 507 command.c:376 register_command(): command 'verify_bank_hash' is already registered in 'esp' context Debug: 107 513 command.c:376 register_command(): command 'flash_stub_clock_boost' is already registered in 'esp' context Debug: 108 519 tcl.c:1319 handle_flash_bank_command(): 'esp32c3' driver usage field missing Debug: 109 523 command.c:146 script_debug(): command - riscv set_reset_timeout_sec 2 Debug: 112 529 command.c:146 script_debug(): command - riscv set_command_timeout_sec 5 Debug: 114 533 command.c:146 script_debug(): command - riscv set_prefer_sba on Debug: 116 537 command.c:146 script_debug(): command - init Debug: 118 539 command.c:146 script_debug(): command - target init Debug: 120 544 command.c:146 script_debug(): command - target names Debug: 121 548 command.c:146 script_debug(): command - esp32c3 cget -event gdb-flash-erase-start Debug: 122 552 command.c:146 script_debug(): command - esp32c3 configure -event gdb-flash-erase-start reset init Debug: 123 559 command.c:146 script_debug(): command - esp32c3 cget -event gdb-flash-write-end Debug: 124 564 command.c:146 script_debug(): command - esp32c3 configure -event gdb-flash-write-end reset halt Debug: 125 569 command.c:146 script_debug(): command - esp32c3 cget -event gdb-attach Debug: 126 576 target.c:1661 handle_target_init_command(): Initializing targets... Debug: 127 580 esp32c3.c:125 esp32c3_init_target(): enter Debug: 128 593 semihosting_common.c:100 semihosting_common_init(): Debug: 129 745 libusb_helper.c:334 jtag_libusb_choose_interface(): usb ep out 02 Debug: 130 750 libusb_helper.c:334 jtag_libusb_choose_interface(): usb ep in 83 Debug: 131 754 libusb_helper.c:342 jtag_libusb_choose_interface(): Claiming interface 2 Info : 132 759 esp_usb_jtag.c:730 esp_usb_jtag_init(): esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255 Debug: 133 766 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 134 771 core.c:1789 adapter_khz_to_speed(): have interface set up Debug: 135 775 esp_usb_jtag.c:789 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1 Debug: 136 781 esp_usb_jtag.c:805 esp_usb_jtag_speed(): esp_usb_jtag: setting divisor 1 Debug: 137 787 core.c:1785 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 138 793 core.c:1789 adapter_khz_to_speed(): have interface set up Debug: 139 797 esp_usb_jtag.c:789 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1 Info : 140 804 core.c:1565 adapter_init(): clock speed 40000 kHz Debug: 141 807 openocd.c:143 handle_init_command(): Debug Adapter init complete Debug: 142 814 command.c:146 script_debug(): command - transport init Debug: 144 817 transport.c:229 handle_transport_init(): handle_transport_init Debug: 145 822 core.c:718 legacy_jtag_add_reset(): SRST line released Debug: 146 825 core.c:742 legacy_jtag_add_reset(): TRST line released Debug: 147 831 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 148 835 command.c:146 script_debug(): command - jtag arp_init Debug: 149 839 core.c:1578 jtag_init_inner(): Init JTAG chain Debug: 150 844 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 151 849 core.c:1243 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS Debug: 152 853 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset Info : 153 859 core.c:1142 jtag_examine_chain_display(): JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0) Debug: 154 867 core.c:1374 jtag_validate_ircapture(): IR capture validation scan Debug: 155 872 core.c:1432 jtag_validate_ircapture(): esp32c3.cpu: IR capture 0x05 Debug: 156 878 command.c:146 script_debug(): command - dap init Debug: 158 881 arm_dap.c:106 dap_init_all(): Initializing all DAPs ... Debug: 159 884 openocd.c:160 handle_init_command(): Examining targets... Debug: 160 889 target.c:1849 target_call_event_callbacks(): target event 19 (examine-start) for core esp32c3 Debug: 161 894 esp32c3.c:113 esp32c3_handle_target_event(): 19 Debug: 162 897 esp_riscv.c:185 esp_riscv_handle_target_event(): 19 Debug: 163 900 riscv.c:976 riscv_examine(): riscv_examine() Debug: 164 904 riscv.c:404 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071 Debug: 165 908 riscv.c:986 riscv_examine(): dtmcontrol=0x1071 Debug: 166 912 riscv.c:988 riscv_examine(): version=0x1 Debug: 167 915 riscv-013.c:2031 init_target(): init Debug: 168 919 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071 Debug: 169 922 riscv-013.c:1585 examine(): dtmcontrol=0x1071 Debug: 170 925 riscv-013.c:1586 examine(): dmireset=0 Debug: 171 928 riscv-013.c:1587 examine(): idle=1 Debug: 172 931 riscv-013.c:1588 examine(): dmistat=0 Debug: 173 935 riscv-013.c:1589 examine(): abits=7 Debug: 174 938 riscv-013.c:1590 examine(): version=1 Debug: 175 941 riscv-013.c:260 get_dm(): [0] Allocating new DM Debug: 176 948 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0 Debug: 177 952 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71 Debug: 178 957 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0 Debug: 179 963 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071 Debug: 180 967 riscv-013.c:1635 examine(): dmstatus: 0x0003cca2 Debug: 181 970 riscv-013.c:1651 examine(): hartsellen=20 Debug: 182 974 riscv-013.c:465 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0 Debug: 183 980 riscv-013.c:454 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071 Debug: 184 984 riscv-013.c:1682 examine(): datacount=2 progbufsize=16 Debug: 185 992 riscv-013.c:1720 examine(): Detected 1 harts. Debug: 186 997 riscv-013.c:3817 select_prepped_harts(): index=0, coreid=0, prepped=0 Debug: 187 1001 riscv-013.c:3858 riscv013_halt_go(): halting hart 0 Debug: 188 1009 riscv-013.c:802 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 189 1018 riscv-013.c:818 execute_abstract_command(): command 0x321008 failed; abstractcs=0x10000202 Debug: 190 1026 riscv-013.c:802 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 191 1037 riscv-013.c:1510 register_read_direct(): {0} misa = 0x40101104 Debug: 192 1040 riscv.c:3819 riscv_init_registers(): create register cache for 4194 registers Debug: 193 1046 riscv-013.c:1778 examine(): hart 0: XLEN=32, misa=0x40101104 Debug: 194 1049 riscv-013.c:4445 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0) Info : 195 1059 riscv-013.c:1802 examine(): Examined RISC-V core; found 1 harts Info : 196 1062 riscv-013.c:1806 examine(): hart 0: XLEN=32, misa=0x40101104 Debug: 197 1067 target.c:1849 target_call_event_callbacks(): target event 21 (examine-end) for core esp32c3 Debug: 198 1071 target.c:4849 target_handle_event(): target(0): esp32c3 (esp32c3) event: 21 (examine-end) action:

Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default

arm semihosting enable
arm semihosting_resexit enable

Debug: 199 1087 command.c:146 script_debug(): command - arm semihosting enable Debug: 201 1091 riscv.c:2039 riscv_poll_hart(): triggered running Debug: 203 1095 riscv_semihosting.c:188 riscv_semihosting_setup(): [esp32c3] enable=1 Debug: 204 1100 command.c:146 script_debug(): command - arm semihosting_resexit enable Debug: 206 1105 esp32c3.c:113 esp32c3_handle_target_event(): 21 Debug: 207 1108 esp_riscv.c:185 esp_riscv_handle_target_event(): 21 Debug: 208 1113 command.c:146 script_debug(): command - flash init Debug: 210 1117 tcl.c:1385 handle_flash_init_command(): Initializing flash devices... Debug: 211 1120 command.c:146 script_debug(): command - nand init Debug: 213 1124 tcl.c:498 handle_nand_init_command(): Initializing NAND devices... Debug: 214 1129 command.c:146 script_debug(): command - pld init Debug: 216 1133 pld.c:206 handle_pld_init_command(): Initializing PLDs... Info : 217 1136 gdb_server.c:3512 gdb_target_start(): starting gdb server for esp32c3 on 3333 Info : 218 1142 server.c:312 add_service(): Listening on port 3333 for gdb connections Debug: 219 1146 command.c:146 script_debug(): command - halt Debug: 221 1150 target.c:3330 handle_halt_command(): - Debug: 222 1153 riscv.c:1092 riscv_halt(): [0] halting all harts Debug: 223 1157 riscv.c:1024 halt_prep(): [esp32c3] prep hart, debug_reason=5 Debug: 224 1162 riscv-013.c:3817 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 225 1167 riscv-013.c:3858 riscv013_halt_go(): halting hart 0 Debug: 226 1174 riscv.c:3209 riscv_invalidate_register_cache(): [0] Debug: 227 1177 target.c:1849 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 228 1181 esp32c3.c:113 esp32c3_handle_target_event(): 0 Debug: 229 1184 esp_riscv.c:185 esp_riscv_handle_target_event(): 0 Debug: 230 1188 target.c:1849 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 231 1193 target.c:4849 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable

Debug: 232 1200 command.c:146 script_debug(): command - command mode Debug: 233 1204 command.c:146 script_debug(): command - mww 0x6001f064 0x50D83AA1 Debug: 235 1211 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 236 1216 command.c:146 script_debug(): command - mww 0x6001F048 0 Debug: 238 1222 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 239 1227 command.c:146 script_debug(): command - mww 0x60020064 0x50D83AA1 Debug: 241 1234 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 242 1239 command.c:146 script_debug(): command - mww 0x60020048 0 Debug: 244 1245 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 245 1251 command.c:146 script_debug(): command - mww 0x600080a8 0x50D83AA1 Debug: 247 1257 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 248 1263 command.c:146 script_debug(): command - mww 0x60008090 0 Debug: 250 1268 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 251 1273 command.c:146 script_debug(): command - mww 0x600080b0 0x8F1D312A Debug: 253 1280 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 254 1286 command.c:146 script_debug(): command - mww 0x600080ac 0x84B00000 Debug: 256 1292 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 257 1298 esp32c3.c:113 esp32c3_handle_target_event(): 1 Debug: 258 1302 esp_riscv.c:185 esp_riscv_handle_target_event(): 1 Debug: 259 1306 command.c:146 script_debug(): command - flash probe 0 Debug: 261 1311 esp_flash.c:929 esp_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32c3' - 'halted' Debug: 262 1315 esp_flash.c:242 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 263 1319 algorithm.c:339 algorithm_load_func_image(): stub: base 0x0, start 0x403816e4, 2 sections Debug: 264 1326 algorithm.c:346 algorithm_load_func_image(): addr 0x00000000, sz 7648, flags 1 Debug: 265 1331 target.c:2043 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x40380000 Debug: 266 1337 target.c:2097 alloc_working_area_try_do(): allocated new working area of 7648 bytes at address 0x40380000 Debug: 267 1344 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:1912 start address: 0x40380000 Debug: 268 1351 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380000 Debug: 269 1357 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380080 Debug: 270 1363 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380100 Debug: 271 1370 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380180 Debug: 272 1375 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380200 Debug: 273 1382 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380280 Debug: 274 1388 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380300 Debug: 275 1394 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380380 Debug: 276 1400 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380400 Debug: 277 1406 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380480 Debug: 278 1412 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380500 Debug: 279 1419 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380580 Debug: 280 1428 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380600 Debug: 281 1434 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380680 Debug: 282 1440 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380700 Debug: 283 1447 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380780 Debug: 284 1453 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380800 Debug: 285 1460 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380880 Debug: 286 1466 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380900 Debug: 287 1472 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380980 Debug: 288 1478 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380a00 Debug: 289 1484 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380a80 Debug: 290 1490 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380b00 Debug: 291 1497 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380b80 Debug: 292 1504 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380c00 Debug: 293 1510 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380c80 Debug: 294 1516 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380d00 Debug: 295 1522 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380d80 Debug: 296 1528 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380e00 Debug: 297 1535 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380e80 Debug: 298 1540 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380f00 Debug: 299 1546 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380f80 Debug: 300 1552 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381000 Debug: 301 1560 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381080 Debug: 302 1566 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381100 Debug: 303 1573 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381180 Debug: 304 1580 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381200 Debug: 305 1587 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381280 Debug: 307 1595 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381300 Debug: 308 1601 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381380 Debug: 309 1610 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381400 Debug: 310 1617 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381480 Debug: 311 1624 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381500 Debug: 312 1630 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381580 Debug: 313 1638 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381600 Debug: 314 1645 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381680 Debug: 315 1651 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381700 Debug: 316 1657 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381780 Debug: 317 1663 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381800 Debug: 318 1671 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381880 Debug: 319 1677 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381900 Debug: 320 1684 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381980 Debug: 321 1690 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381a00 Debug: 322 1696 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381a80 Debug: 323 1702 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381b00 Debug: 324 1707 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381b80 Debug: 325 1714 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381c00 Debug: 326 1720 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381c80 Debug: 327 1726 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381d00 Debug: 328 1733 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381d80 Debug: 329 1739 target.c:1964 print_wa_layout(): b* 0x40380000-0x40381ddf (7648 bytes) Debug: 330 1744 target.c:1964 print_wa_layout(): 0x40381de0-0x40383fff (8736 bytes) Debug: 331 1748 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380000 Debug: 332 1754 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 333 1762 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 334 1768 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 335 1777 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 336 1783 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380200 Debug: 337 1789 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 338 1796 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 339 1803 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 340 1810 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 341 1816 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380400 Debug: 342 1822 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 343 1828 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 344 1836 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 345 1843 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 346 1850 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380600 Debug: 347 1856 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 348 1863 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 349 1869 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 350 1876 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 351 1883 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380800 Debug: 352 1888 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 353 1896 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 354 1902 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 355 1910 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 356 1917 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380a00 Debug: 357 1923 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 358 1929 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 359 1935 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 360 1944 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 361 1950 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380c00 Debug: 362 1956 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 363 1963 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 364 1970 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 365 1977 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 366 1984 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380e00 Debug: 367 1990 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 368 1996 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 369 2003 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 370 2010 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 371 2017 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381000 Debug: 372 2024 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 373 2031 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 374 2037 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 375 2045 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 376 2053 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381200 Debug: 377 2061 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 378 2067 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 379 2074 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 380 2081 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 381 2089 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381400 Debug: 382 2095 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 384 2102 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 385 2108 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 386 2115 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 387 2123 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381600 Debug: 388 2129 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 389 2137 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 390 2144 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 391 2153 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 392 2160 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381800 Debug: 393 2167 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 394 2174 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 395 2181 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 396 2187 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 397 2194 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381a00 Debug: 398 2199 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 399 2206 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 400 2213 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 401 2220 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 402 2227 target.c:2445 target_write_buffer(): writing buffer of 480 byte at 0x40381c00 Debug: 403 2233 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 404 2240 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 405 2246 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 406 2254 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 407 2260 algorithm.c:346 algorithm_load_func_image(): addr 0x00000000, sz 637, flags 0 Debug: 408 2265 algorithm.c:376 algorithm_load_func_image(): DATA sec size 637 -> 640 Debug: 409 2271 algorithm.c:379 algorithm_load_func_image(): BSS sec size 289 -> 292 Debug: 410 2276 target.c:2043 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x3fc84000 Debug: 411 2285 target.c:2097 alloc_working_area_try_do(): allocated new working area of 932 bytes at address 0x3fc84000 Debug: 412 2292 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:233 start address: 0x3fc84000 Debug: 413 2301 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84000 Debug: 414 2306 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84080 Debug: 415 2313 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84100 Debug: 416 2319 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84180 Debug: 417 2324 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84200 Debug: 418 2332 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84280 Debug: 419 2339 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84300 Debug: 420 2347 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84380 Debug: 421 2352 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 422 2356 target.c:1964 print_wa_layout(): 0x3fc843a4-0x3fca3fff (130140 bytes) Debug: 423 2360 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000 Debug: 424 2366 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 425 2374 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 426 2381 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 427 2389 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 428 2396 target.c:2445 target_write_buffer(): writing buffer of 125 byte at 0x3fc84200 Debug: 429 2401 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 430 2407 riscv-013.c:3447 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc8427c Debug: 431 2413 riscv-013.c:802 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 432 2423 riscv-013.c:1510 register_read_direct(): {0} s0 = 0x600d0170 Debug: 433 2427 riscv-013.c:802 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 434 2437 riscv-013.c:1510 register_read_direct(): {0} s1 = 0x1 Debug: 435 2440 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x00940023) Debug: 436 2444 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x00140413) Debug: 437 2450 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 438 2455 riscv-013.c:3504 write_memory_progbuf(): writing until final address 0x000000003fc8427d Debug: 439 2461 riscv-013.c:3507 write_memory_progbuf(): transferring burst starting at address 0x000000003fc8427c Debug: 440 2466 riscv-013.c:1320 register_write_direct(): {0} s0 <- 0x3fc8427c Debug: 441 2471 riscv-013.c:802 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 442 2480 riscv-013.c:802 execute_abstract_command(): command=0x271009; access register, size=32, postexec=1, transfer=1, write=1, regno=0x1009 Debug: 443 2490 batch.c:81 riscv_batch_run(): Ignoring empty batch. Debug: 444 2494 riscv-013.c:3587 write_memory_progbuf(): successful (partial?) memory write Debug: 445 2499 riscv-013.c:1320 register_write_direct(): {0} s1 <- 0x1 Debug: 446 2502 riscv-013.c:802 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 447 2512 riscv-013.c:1320 register_write_direct(): {0} s0 <- 0x600d0170 Debug: 448 2516 riscv-013.c:802 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 449 2526 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 450 2532 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 451 2538 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 452 2542 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 453 2546 riscv-013.c:802 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 454 2554 target.c:2097 alloc_working_area_try_do(): allocated new working area of 1300 bytes at address 0x3fc843a4 Debug: 455 2562 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:325 start address: 0x3fc843a4 Debug: 456 2570 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc843a4 Debug: 457 2575 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84424 Debug: 458 2581 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc844a4 Debug: 459 2587 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84524 Debug: 460 2594 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc845a4 Debug: 461 2602 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84624 Debug: 463 2607 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc846a4 Debug: 464 2614 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84724 Debug: 465 2619 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc847a4 Debug: 466 2625 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84824 Debug: 467 2632 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc848a4 Debug: 468 2639 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 469 2644 target.c:1964 print_wa_layout(): b 0x3fc843a4-0x3fc848b7 (1300 bytes) Debug: 470 2649 target.c:1964 print_wa_layout(): 0x3fc848b8-0x3fca3fff (128840 bytes) Debug: 471 2654 target.c:2097 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381de0 Debug: 472 2661 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:1 start address: 0x40381de0 Debug: 473 2670 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381de0 Debug: 474 2677 target.c:1964 print_wa_layout(): b 0x40380000-0x40381ddf (7648 bytes) Debug: 475 2680 target.c:1964 print_wa_layout(): b 0x40381de0-0x40381de3 (4 bytes) Debug: 476 2686 target.c:1964 print_wa_layout(): 0x40381de4-0x40383fff (8732 bytes) Debug: 477 2691 target.c:2445 target_write_buffer(): writing buffer of 4 byte at 0x40381de0 Debug: 478 2698 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381de0 Debug: 479 2704 algorithm.c:462 algorithm_load_func_image(): Stub loaded in 1385.18 ms Debug: 480 2708 riscv_algorithm.c:53 riscv_algo_regs_init_start(): Check stack addr 0x3fc848b8 Debug: 481 2712 riscv_algorithm.c:56 riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc848b0 Debug: 482 2718 riscv_algorithm.c:96 riscv_algo_init(): Set arg[0] = 5 (a0) Debug: 483 2722 riscv_algorithm.c:106 riscv_algo_init(): Set arg[1] = -1 (a1) Debug: 484 2725 riscv_algorithm.c:106 riscv_algo_init(): Set arg[2] = 0 (a2) Debug: 485 2729 target.c:2097 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x3fc848b8 Debug: 486 2735 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:7 start address: 0x3fc848b8 Debug: 487 2741 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc848b8 Debug: 488 2747 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 489 2751 target.c:1964 print_wa_layout(): b 0x3fc843a4-0x3fc848b7 (1300 bytes) Debug: 490 2755 target.c:1964 print_wa_layout(): b 0x3fc848b8-0x3fc848d3 (28 bytes) Debug: 491 2759 target.c:1964 print_wa_layout(): 0x3fc848d4-0x3fca3fff (128812 bytes) Debug: 492 2764 algorithm.c:224 algorithm_run(): Algorithm start @ 0x40381de0, stack 1300 bytes @ 0x3fc848b8 Debug: 493 2769 riscv.c:1773 riscv_start_algorithm(): save ra Debug: 494 2772 riscv-013.c:3715 riscv013_get_register(): [0] reading register ra on hart 0 Debug: 495 2777 riscv-013.c:802 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001 Debug: 496 2786 riscv-013.c:1510 register_read_direct(): {0} ra = 0x0 Debug: 497 2789 riscv.c:3374 riscv_get_register_on_hart(): {0} ra: 0 Debug: 498 2793 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from ra (valid=1) Debug: 499 2797 riscv.c:1773 riscv_start_algorithm(): save sp Debug: 500 2800 riscv-013.c:3715 riscv013_get_register(): [0] reading register sp on hart 0 Debug: 501 2805 riscv-013.c:802 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002 Debug: 502 2818 riscv-013.c:1510 register_read_direct(): {0} sp = 0x600d00c0 Debug: 503 2821 riscv.c:3374 riscv_get_register_on_hart(): {0} sp: 600d00c0 Debug: 504 2826 riscv.c:3734 register_get(): [0]{0} read 0x600d00c0 from sp (valid=1) Debug: 505 2831 riscv.c:1773 riscv_start_algorithm(): save gp Debug: 506 2835 riscv-013.c:3715 riscv013_get_register(): [0] reading register gp on hart 0 Debug: 507 2842 riscv-013.c:802 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003 Debug: 508 2850 riscv-013.c:1510 register_read_direct(): {0} gp = 0x3fc8aa00 Debug: 509 2854 riscv.c:3374 riscv_get_register_on_hart(): {0} gp: 3fc8aa00 Debug: 510 2859 riscv.c:3734 register_get(): [0]{0} read 0x3fc8aa00 from gp (valid=1) Debug: 511 2862 riscv.c:1773 riscv_start_algorithm(): save tp Debug: 512 2865 riscv-013.c:3715 riscv013_get_register(): [0] reading register tp on hart 0 Debug: 513 2870 riscv-013.c:802 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004 Debug: 514 2879 riscv-013.c:1510 register_read_direct(): {0} tp = 0x3fc890f0 Debug: 515 2883 riscv.c:3374 riscv_get_register_on_hart(): {0} tp: 3fc890f0 Debug: 516 2887 riscv.c:3734 register_get(): [0]{0} read 0x3fc890f0 from tp (valid=1) Debug: 517 2891 riscv.c:1773 riscv_start_algorithm(): save t0 Debug: 518 2894 riscv-013.c:3715 riscv013_get_register(): [0] reading register t0 on hart 0 Debug: 519 2899 riscv-013.c:802 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005 Debug: 520 2907 riscv-013.c:1510 register_read_direct(): {0} t0 = 0x80000000 Debug: 521 2911 riscv.c:3374 riscv_get_register_on_hart(): {0} t0: 80000000 Debug: 522 2916 riscv.c:3734 register_get(): [0]{0} read 0x80000000 from t0 (valid=1) Debug: 523 2920 riscv.c:1773 riscv_start_algorithm(): save t1 Debug: 524 2924 riscv-013.c:3715 riscv013_get_register(): [0] reading register t1 on hart 0 Debug: 525 2929 riscv-013.c:802 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006 Debug: 526 2938 riscv-013.c:1510 register_read_direct(): {0} t1 = 0x400510a0 Debug: 527 2943 riscv.c:3374 riscv_get_register_on_hart(): {0} t1: 400510a0 Debug: 528 2946 riscv.c:3734 register_get(): [0]{0} read 0x400510a0 from t1 (valid=1) Debug: 529 2951 riscv.c:1773 riscv_start_algorithm(): save t2 Debug: 530 2955 riscv-013.c:3715 riscv013_get_register(): [0] reading register t2 on hart 0 Debug: 531 2962 riscv-013.c:802 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007 Debug: 532 2970 riscv-013.c:1510 register_read_direct(): {0} t2 = 0x0 Debug: 533 2975 riscv.c:3374 riscv_get_register_on_hart(): {0} t2: 0 Debug: 534 2978 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from t2 (valid=1) Debug: 535 2982 riscv.c:1773 riscv_start_algorithm(): save fp Debug: 536 2985 riscv-013.c:3715 riscv013_get_register(): [0] reading register s0 on hart 0 Debug: 537 2990 riscv-013.c:802 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 538 3000 riscv-013.c:1510 register_read_direct(): {0} s0 = 0x600d0170 Debug: 539 3004 riscv.c:3374 riscv_get_register_on_hart(): {0} s0: 600d0170 Debug: 540 3008 riscv.c:3734 register_get(): [0]{0} read 0x600d0170 from fp (valid=1) Debug: 541 3013 riscv.c:1773 riscv_start_algorithm(): save s1 Debug: 542 3015 riscv-013.c:3715 riscv013_get_register(): [0] reading register s1 on hart 0 Debug: 543 3020 riscv-013.c:802 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 544 3029 riscv-013.c:1510 register_read_direct(): {0} s1 = 0x1 Debug: 545 3032 riscv.c:3374 riscv_get_register_on_hart(): {0} s1: 1 Debug: 546 3037 riscv.c:3734 register_get(): [0]{0} read 0x00000001 from s1 (valid=1) Debug: 547 3042 riscv.c:1773 riscv_start_algorithm(): save a0 Debug: 548 3045 riscv-013.c:3715 riscv013_get_register(): [0] reading register a0 on hart 0 Debug: 549 3050 riscv-013.c:802 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 550 3059 riscv-013.c:1510 register_read_direct(): {0} a0 = 0x600d00c0 Debug: 551 3062 riscv.c:3374 riscv_get_register_on_hart(): {0} a0: 600d00c0 Debug: 552 3067 riscv.c:3734 register_get(): [0]{0} read 0x600d00c0 from a0 (valid=1) Debug: 553 3071 riscv.c:1773 riscv_start_algorithm(): save a1 Debug: 554 3075 riscv-013.c:3715 riscv013_get_register(): [0] reading register a1 on hart 0 Debug: 555 3080 riscv-013.c:802 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b Debug: 556 3089 riscv-013.c:1510 register_read_direct(): {0} a1 = 0x1 Debug: 557 3092 riscv.c:3374 riscv_get_register_on_hart(): {0} a1: 1 Debug: 558 3097 riscv.c:3734 register_get(): [0]{0} read 0x00000001 from a1 (valid=1) Debug: 559 3102 riscv.c:1773 riscv_start_algorithm(): save a2 Debug: 560 3106 riscv-013.c:3715 riscv013_get_register(): [0] reading register a2 on hart 0 Debug: 561 3112 riscv-013.c:802 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c Debug: 562 3121 riscv-013.c:1510 register_read_direct(): {0} a2 = 0x3fc848b8 Debug: 563 3124 riscv.c:3374 riscv_get_register_on_hart(): {0} a2: 3fc848b8 Debug: 564 3130 riscv.c:3734 register_get(): [0]{0} read 0x3fc848b8 from a2 (valid=1) Debug: 565 3134 riscv.c:1773 riscv_start_algorithm(): save a3 Debug: 566 3137 riscv-013.c:3715 riscv013_get_register(): [0] reading register a3 on hart 0 Debug: 567 3143 riscv-013.c:802 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d Debug: 568 3153 riscv-013.c:1510 register_read_direct(): {0} a3 = 0x4 Debug: 569 3157 riscv.c:3374 riscv_get_register_on_hart(): {0} a3: 4 Debug: 570 3161 riscv.c:3734 register_get(): [0]{0} read 0x00000004 from a3 (valid=1) Debug: 571 3165 riscv.c:1773 riscv_start_algorithm(): save a4 Debug: 572 3168 riscv-013.c:3715 riscv013_get_register(): [0] reading register a4 on hart 0 Debug: 573 3173 riscv-013.c:802 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e Debug: 574 3181 riscv-013.c:1510 register_read_direct(): {0} a4 = 0x600c4000 Debug: 575 3185 riscv.c:3374 riscv_get_register_on_hart(): {0} a4: 600c4000 Debug: 576 3190 riscv.c:3734 register_get(): [0]{0} read 0x600c4000 from a4 (valid=1) Debug: 577 3194 riscv.c:1773 riscv_start_algorithm(): save a5 Debug: 578 3197 riscv-013.c:3715 riscv013_get_register(): [0] reading register a5 on hart 0 Debug: 579 3202 riscv-013.c:802 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f Debug: 580 3211 riscv-013.c:1510 register_read_direct(): {0} a5 = 0x600c4000 Debug: 581 3214 riscv.c:3374 riscv_get_register_on_hart(): {0} a5: 600c4000 Debug: 582 3218 riscv.c:3734 register_get(): [0]{0} read 0x600c4000 from a5 (valid=1) Debug: 583 3222 riscv.c:1773 riscv_start_algorithm(): save a6 Debug: 584 3227 riscv-013.c:3715 riscv013_get_register(): [0] reading register a6 on hart 0 Debug: 585 3231 riscv-013.c:802 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010 Debug: 586 3240 riscv-013.c:1510 register_read_direct(): {0} a6 = 0x0 Debug: 587 3243 riscv.c:3374 riscv_get_register_on_hart(): {0} a6: 0 Debug: 588 3246 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from a6 (valid=1) Debug: 589 3252 riscv.c:1773 riscv_start_algorithm(): save a7 Debug: 590 3255 riscv-013.c:3715 riscv013_get_register(): [0] reading register a7 on hart 0 Debug: 591 3261 riscv-013.c:802 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011 Debug: 592 3271 riscv-013.c:1510 register_read_direct(): {0} a7 = 0x403816e4 Debug: 593 3275 riscv.c:3374 riscv_get_register_on_hart(): {0} a7: 403816e4 Debug: 594 3279 riscv.c:3734 register_get(): [0]{0} read 0x403816e4 from a7 (valid=1) Debug: 595 3284 riscv.c:1773 riscv_start_algorithm(): save s2 Debug: 596 3287 riscv-013.c:3715 riscv013_get_register(): [0] reading register s2 on hart 0 Debug: 597 3292 riscv-013.c:802 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012 Debug: 598 3302 riscv-013.c:1510 register_read_direct(): {0} s2 = 0x0 Debug: 599 3305 riscv.c:3374 riscv_get_register_on_hart(): {0} s2: 0 Debug: 600 3308 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s2 (valid=1) Debug: 601 3314 riscv.c:1773 riscv_start_algorithm(): save s3 Debug: 602 3318 riscv-013.c:3715 riscv013_get_register(): [0] reading register s3 on hart 0 Debug: 603 3323 riscv-013.c:802 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013 Debug: 604 3335 riscv-013.c:1510 register_read_direct(): {0} s3 = 0x0 Debug: 605 3337 riscv.c:3374 riscv_get_register_on_hart(): {0} s3: 0 Debug: 606 3342 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s3 (valid=1) Debug: 607 3346 riscv.c:1773 riscv_start_algorithm(): save s4 Debug: 608 3349 riscv-013.c:3715 riscv013_get_register(): [0] reading register s4 on hart 0 Debug: 609 3354 riscv-013.c:802 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014 Debug: 610 3365 riscv-013.c:1510 register_read_direct(): {0} s4 = 0x0 Debug: 611 3368 riscv.c:3374 riscv_get_register_on_hart(): {0} s4: 0 Debug: 612 3372 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s4 (valid=1) Debug: 613 3377 riscv.c:1773 riscv_start_algorithm(): save s5 Debug: 614 3380 riscv-013.c:3715 riscv013_get_register(): [0] reading register s5 on hart 0 Debug: 615 3385 riscv-013.c:802 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015 Debug: 616 3395 riscv-013.c:1510 register_read_direct(): {0} s5 = 0x0 Debug: 617 3399 riscv.c:3374 riscv_get_register_on_hart(): {0} s5: 0 Debug: 618 3403 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s5 (valid=1) Debug: 619 3407 riscv.c:1773 riscv_start_algorithm(): save s6 Debug: 620 3410 riscv-013.c:3715 riscv013_get_register(): [0] reading register s6 on hart 0 Debug: 621 3414 riscv-013.c:802 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016 Debug: 622 3424 riscv-013.c:1510 register_read_direct(): {0} s6 = 0x0 Debug: 623 3427 riscv.c:3374 riscv_get_register_on_hart(): {0} s6: 0 Debug: 624 3432 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s6 (valid=1) Debug: 625 3437 riscv.c:1773 riscv_start_algorithm(): save s7 Debug: 626 3441 riscv-013.c:3715 riscv013_get_register(): [0] reading register s7 on hart 0 Debug: 627 3446 riscv-013.c:802 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017 Debug: 628 3456 riscv-013.c:1510 register_read_direct(): {0} s7 = 0x0 Debug: 629 3459 riscv.c:3374 riscv_get_register_on_hart(): {0} s7: 0 Debug: 630 3463 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s7 (valid=1) Debug: 631 3467 riscv.c:1773 riscv_start_algorithm(): save s8 Debug: 632 3470 riscv-013.c:3715 riscv013_get_register(): [0] reading register s8 on hart 0 Debug: 633 3474 riscv-013.c:802 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018 Debug: 634 3486 riscv-013.c:1510 register_read_direct(): {0} s8 = 0x0 Debug: 635 3489 riscv.c:3374 riscv_get_register_on_hart(): {0} s8: 0 Debug: 636 3493 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s8 (valid=1) Debug: 637 3497 riscv.c:1773 riscv_start_algorithm(): save s9 Debug: 638 3500 riscv-013.c:3715 riscv013_get_register(): [0] reading register s9 on hart 0 Debug: 639 3504 riscv-013.c:802 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019 Debug: 640 3514 riscv-013.c:1510 register_read_direct(): {0} s9 = 0x0 Debug: 641 3517 riscv.c:3374 riscv_get_register_on_hart(): {0} s9: 0 Debug: 642 3520 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s9 (valid=1) Debug: 643 3526 riscv.c:1773 riscv_start_algorithm(): save s10 Debug: 644 3529 riscv-013.c:3715 riscv013_get_register(): [0] reading register s10 on hart 0 Debug: 645 3534 riscv-013.c:802 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a Debug: 646 3546 riscv-013.c:1510 register_read_direct(): {0} s10 = 0x0 Debug: 647 3548 riscv.c:3374 riscv_get_register_on_hart(): {0} s10: 0 Debug: 648 3553 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s10 (valid=1) Debug: 649 3557 riscv.c:1773 riscv_start_algorithm(): save s11 Debug: 650 3561 riscv-013.c:3715 riscv013_get_register(): [0] reading register s11 on hart 0 Debug: 651 3567 riscv-013.c:802 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b Debug: 652 3576 riscv-013.c:1510 register_read_direct(): {0} s11 = 0x0 Debug: 653 3579 riscv.c:3374 riscv_get_register_on_hart(): {0} s11: 0 Debug: 654 3583 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from s11 (valid=1) Debug: 655 3588 riscv.c:1773 riscv_start_algorithm(): save t3 Debug: 656 3592 riscv-013.c:3715 riscv013_get_register(): [0] reading register t3 on hart 0 Debug: 657 3596 riscv-013.c:802 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c Debug: 658 3606 riscv-013.c:1510 register_read_direct(): {0} t3 = 0x0 Debug: 659 3609 riscv.c:3374 riscv_get_register_on_hart(): {0} t3: 0 Debug: 660 3614 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from t3 (valid=1) Debug: 661 3617 riscv.c:1773 riscv_start_algorithm(): save t4 Debug: 662 3621 riscv-013.c:3715 riscv013_get_register(): [0] reading register t4 on hart 0 Debug: 663 3626 riscv-013.c:802 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d Debug: 664 3635 riscv-013.c:1510 register_read_direct(): {0} t4 = 0x0 Debug: 665 3638 riscv.c:3374 riscv_get_register_on_hart(): {0} t4: 0 Debug: 666 3642 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from t4 (valid=1) Debug: 667 3647 riscv.c:1773 riscv_start_algorithm(): save t5 Debug: 668 3650 riscv-013.c:3715 riscv013_get_register(): [0] reading register t5 on hart 0 Debug: 669 3655 riscv-013.c:802 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e Debug: 670 3666 riscv-013.c:1510 register_read_direct(): {0} t5 = 0x0 Debug: 671 3669 riscv.c:3374 riscv_get_register_on_hart(): {0} t5: 0 Debug: 672 3672 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from t5 (valid=1) Debug: 673 3678 riscv.c:1773 riscv_start_algorithm(): save t6 Debug: 674 3682 riscv-013.c:3715 riscv013_get_register(): [0] reading register t6 on hart 0 Debug: 675 3687 riscv-013.c:802 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f Debug: 676 3697 riscv-013.c:1510 register_read_direct(): {0} t6 = 0x0 Debug: 677 3701 riscv.c:3374 riscv_get_register_on_hart(): {0} t6: 0 Debug: 678 3705 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from t6 (valid=1) Debug: 679 3710 riscv.c:1773 riscv_start_algorithm(): save pc Debug: 680 3714 riscv-013.c:3715 riscv013_get_register(): [0] reading register pc on hart 0 Debug: 681 3718 riscv-013.c:802 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 682 3729 riscv-013.c:1510 register_read_direct(): {0} dpc = 0x40380000 Debug: 683 3732 riscv-013.c:3723 riscv013_get_register(): [0] read PC from DPC: 0x40380000 Debug: 684 3738 riscv.c:3374 riscv_get_register_on_hart(): {0} pc: 40380000 Debug: 685 3745 riscv.c:3734 register_get(): [0]{0} read 0x40380000 from pc (valid=0) Debug: 686 3750 riscv.c:1773 riscv_start_algorithm(): save ustatus Debug: 687 3753 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr0 on hart 0 Debug: 688 3758 riscv-013.c:802 execute_abstract_command(): command=0x220000; access register, size=32, postexec=0, transfer=1, write=0, regno=0x0 Debug: 689 3769 riscv-013.c:1510 register_read_direct(): {0} csr0 = 0x0 Debug: 690 3772 riscv.c:3374 riscv_get_register_on_hart(): {0} csr0: 0 Debug: 691 3775 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from ustatus (valid=0) Debug: 692 3780 riscv.c:1773 riscv_start_algorithm(): save uepc Debug: 693 3783 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr65 on hart 0 Debug: 694 3787 riscv-013.c:802 execute_abstract_command(): command=0x220041; access register, size=32, postexec=0, transfer=1, write=0, regno=0x41 Debug: 695 3797 riscv-013.c:1510 register_read_direct(): {0} csr65 = 0x0 Debug: 696 3801 riscv.c:3374 riscv_get_register_on_hart(): {0} csr65: 0 Debug: 697 3805 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from uepc (valid=0) Debug: 698 3809 riscv.c:1773 riscv_start_algorithm(): save ucause Debug: 699 3813 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr66 on hart 0 Debug: 700 3818 riscv-013.c:802 execute_abstract_command(): command=0x220042; access register, size=32, postexec=0, transfer=1, write=0, regno=0x42 Debug: 701 3827 riscv-013.c:1510 register_read_direct(): {0} csr66 = 0x0 Debug: 702 3830 riscv.c:3374 riscv_get_register_on_hart(): {0} csr66: 0 Debug: 703 3834 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from ucause (valid=0) Debug: 704 3838 riscv.c:1773 riscv_start_algorithm(): save mstatus Debug: 705 3842 riscv-013.c:3715 riscv013_get_register(): [0] reading register mstatus on hart 0 Debug: 706 3848 riscv-013.c:802 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 707 3860 riscv-013.c:1510 register_read_direct(): {0} mstatus = 0x1800 Debug: 708 3863 riscv.c:3374 riscv_get_register_on_hart(): {0} mstatus: 1800 Debug: 709 3867 riscv.c:3734 register_get(): [0]{0} read 0x00001800 from mstatus (valid=1) Debug: 710 3872 riscv.c:1773 riscv_start_algorithm(): save misa Debug: 711 3875 riscv-013.c:3715 riscv013_get_register(): [0] reading register misa on hart 0 Debug: 712 3880 riscv-013.c:802 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301 Debug: 713 3889 riscv-013.c:1510 register_read_direct(): {0} misa = 0x40101104 Debug: 714 3894 riscv.c:3374 riscv_get_register_on_hart(): {0} misa: 40101104 Debug: 715 3898 riscv.c:3734 register_get(): [0]{0} read 0x40101104 from misa (valid=1) Debug: 716 3903 riscv.c:1773 riscv_start_algorithm(): save mtvec Debug: 717 3906 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr773 on hart 0 Debug: 718 3910 riscv-013.c:802 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305 Debug: 719 3920 riscv-013.c:1510 register_read_direct(): {0} csr773 = 0x40380001 Debug: 720 3925 riscv.c:3374 riscv_get_register_on_hart(): {0} csr773: 40380001 Debug: 721 3929 riscv.c:3734 register_get(): [0]{0} read 0x40380001 from mtvec (valid=0) Debug: 722 3934 riscv.c:1773 riscv_start_algorithm(): save mscratch Debug: 723 3937 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr832 on hart 0 Debug: 724 3943 riscv-013.c:802 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340 Debug: 725 3952 riscv-013.c:1510 register_read_direct(): {0} csr832 = 0x0 Debug: 726 3955 riscv.c:3374 riscv_get_register_on_hart(): {0} csr832: 0 Debug: 727 3959 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from mscratch (valid=0) Debug: 728 3964 riscv.c:1773 riscv_start_algorithm(): save mepc Debug: 729 3967 riscv-013.c:3715 riscv013_get_register(): [0] reading register mepc on hart 0 Debug: 730 3972 riscv-013.c:802 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 731 3982 riscv-013.c:1510 register_read_direct(): {0} mepc = 0x40380000 Debug: 732 3985 riscv.c:3374 riscv_get_register_on_hart(): {0} mepc: 40380000 Debug: 733 3989 riscv.c:3734 register_get(): [0]{0} read 0x40380000 from mepc (valid=1) Debug: 734 3994 riscv.c:1773 riscv_start_algorithm(): save mcause Debug: 735 3997 riscv-013.c:3715 riscv013_get_register(): [0] reading register mcause on hart 0 Debug: 736 4002 riscv-013.c:802 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 737 4012 riscv-013.c:1510 register_read_direct(): {0} mcause = 0x2 Debug: 738 4015 riscv.c:3374 riscv_get_register_on_hart(): {0} mcause: 2 Debug: 739 4018 riscv.c:3734 register_get(): [0]{0} read 0x00000002 from mcause (valid=1) Debug: 740 4023 riscv.c:1773 riscv_start_algorithm(): save mtval Debug: 741 4027 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr835 on hart 0 Debug: 742 4031 riscv-013.c:802 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343 Debug: 743 4041 riscv-013.c:1510 register_read_direct(): {0} csr835 = 0x0 Debug: 744 4045 riscv.c:3374 riscv_get_register_on_hart(): {0} csr835: 0 Debug: 745 4049 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from mtval (valid=0) Debug: 746 4054 riscv.c:1773 riscv_start_algorithm(): save pmpcfg0 Debug: 747 4057 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr928 on hart 0 Debug: 748 4062 riscv-013.c:802 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0 Debug: 749 4071 riscv-013.c:1510 register_read_direct(): {0} csr928 = 0x89888f88 Debug: 750 4076 riscv.c:3374 riscv_get_register_on_hart(): {0} csr928: 89888f88 Debug: 751 4081 riscv.c:3734 register_get(): [0]{0} read 0x89888f88 from pmpcfg0 (valid=0) Debug: 752 4085 riscv.c:1773 riscv_start_algorithm(): save pmpcfg1 Debug: 753 4089 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr929 on hart 0 Debug: 754 4094 riscv-013.c:802 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1 Debug: 755 4103 riscv-013.c:1510 register_read_direct(): {0} csr929 = 0x888d898b Debug: 756 4106 riscv.c:3374 riscv_get_register_on_hart(): {0} csr929: 888d898b Debug: 757 4110 riscv.c:3734 register_get(): [0]{0} read 0x888d898b from pmpcfg1 (valid=0) Debug: 758 4116 riscv.c:1773 riscv_start_algorithm(): save pmpcfg2 Debug: 759 4120 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr930 on hart 0 Debug: 760 4128 riscv-013.c:802 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2 Debug: 761 4136 riscv-013.c:1510 register_read_direct(): {0} csr930 = 0x8f888d8f Debug: 762 4140 riscv.c:3374 riscv_get_register_on_hart(): {0} csr930: 8f888d8f Debug: 763 4145 riscv.c:3734 register_get(): [0]{0} read 0x8f888d8f from pmpcfg2 (valid=0) Debug: 764 4149 riscv.c:1773 riscv_start_algorithm(): save pmpcfg3 Debug: 765 4152 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr931 on hart 0 Debug: 766 4158 riscv-013.c:802 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3 Debug: 767 4167 riscv-013.c:1510 register_read_direct(): {0} csr931 = 0x90888b88 Debug: 768 4170 riscv.c:3374 riscv_get_register_on_hart(): {0} csr931: 90888b88 Debug: 769 4176 riscv.c:3734 register_get(): [0]{0} read 0x90888b88 from pmpcfg3 (valid=0) Debug: 770 4181 riscv.c:1773 riscv_start_algorithm(): save pmpaddr0 Debug: 771 4185 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr944 on hart 0 Debug: 772 4191 riscv-013.c:802 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0 Debug: 773 4200 riscv-013.c:1510 register_read_direct(): {0} csr944 = 0x8000000 Debug: 774 4204 riscv.c:3374 riscv_get_register_on_hart(): {0} csr944: 8000000 Debug: 775 4207 riscv.c:3734 register_get(): [0]{0} read 0x08000000 from pmpaddr0 (valid=0) Debug: 776 4212 riscv.c:1773 riscv_start_algorithm(): save pmpaddr1 Debug: 777 4217 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr945 on hart 0 Debug: 778 4221 riscv-013.c:802 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1 Debug: 779 4230 riscv-013.c:1510 register_read_direct(): {0} csr945 = 0xa000000 Debug: 780 4234 riscv.c:3374 riscv_get_register_on_hart(): {0} csr945: a000000 Debug: 781 4238 riscv.c:3734 register_get(): [0]{0} read 0x0a000000 from pmpaddr1 (valid=0) Debug: 782 4242 riscv.c:1773 riscv_start_algorithm(): save pmpaddr2 Debug: 783 4247 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr946 on hart 0 Debug: 784 4252 riscv-013.c:802 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2 Debug: 785 4260 riscv-013.c:1510 register_read_direct(): {0} csr946 = 0xf000000 Debug: 786 4265 riscv.c:3374 riscv_get_register_on_hart(): {0} csr946: f000000 Debug: 787 4268 riscv.c:3734 register_get(): [0]{0} read 0x0f000000 from pmpaddr2 (valid=0) Debug: 788 4273 riscv.c:1773 riscv_start_algorithm(): save pmpaddr3 Debug: 789 4276 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr947 on hart 0 Debug: 790 4281 riscv-013.c:802 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3 Debug: 791 4290 riscv-013.c:1510 register_read_direct(): {0} csr947 = 0xff20000 Debug: 792 4295 riscv.c:3374 riscv_get_register_on_hart(): {0} csr947: ff20000 Debug: 793 4298 riscv.c:3734 register_get(): [0]{0} read 0x0ff20000 from pmpaddr3 (valid=0) Debug: 794 4303 riscv.c:1773 riscv_start_algorithm(): save pmpaddr4 Debug: 795 4306 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr948 on hart 0 Debug: 796 4312 riscv-013.c:802 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4 Debug: 797 4320 riscv-013.c:1510 register_read_direct(): {0} csr948 = 0xff38000 Debug: 798 4325 riscv.c:3374 riscv_get_register_on_hart(): {0} csr948: ff38000 Debug: 799 4329 riscv.c:3734 register_get(): [0]{0} read 0x0ff38000 from pmpaddr4 (valid=0) Debug: 800 4333 riscv.c:1773 riscv_start_algorithm(): save pmpaddr5 Debug: 801 4337 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr949 on hart 0 Debug: 802 4342 riscv-013.c:802 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5 Debug: 803 4350 riscv-013.c:1510 register_read_direct(): {0} csr949 = 0xffc8000 Debug: 804 4354 riscv.c:3374 riscv_get_register_on_hart(): {0} csr949: ffc8000 Debug: 805 4358 riscv.c:3734 register_get(): [0]{0} read 0x0ffc8000 from pmpaddr5 (valid=0) Debug: 806 4362 riscv.c:1773 riscv_start_algorithm(): save pmpaddr6 Debug: 807 4365 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr950 on hart 0 Debug: 808 4371 riscv-013.c:802 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6 Debug: 809 4381 riscv-013.c:1510 register_read_direct(): {0} csr950 = 0x10018000 Debug: 810 4386 riscv.c:3374 riscv_get_register_on_hart(): {0} csr950: 10018000 Debug: 811 4389 riscv.c:3734 register_get(): [0]{0} read 0x10018000 from pmpaddr6 (valid=0) Debug: 812 4394 riscv.c:1773 riscv_start_algorithm(): save pmpaddr7 Debug: 813 4397 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr951 on hart 0 Debug: 814 4402 riscv-013.c:802 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7 Debug: 815 4413 riscv-013.c:1510 register_read_direct(): {0} csr951 = 0x100df000 Debug: 816 4418 riscv.c:3374 riscv_get_register_on_hart(): {0} csr951: 100df000 Debug: 817 4422 riscv.c:3734 register_get(): [0]{0} read 0x100df000 from pmpaddr7 (valid=0) Debug: 818 4427 riscv.c:1773 riscv_start_algorithm(): save pmpaddr8 Debug: 819 4431 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr952 on hart 0 Debug: 820 4435 riscv-013.c:802 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8 Debug: 821 4445 riscv-013.c:1510 register_read_direct(): {0} csr952 = 0x100f8000 Debug: 822 4448 riscv.c:3374 riscv_get_register_on_hart(): {0} csr952: 100f8000 Debug: 823 4452 riscv.c:3734 register_get(): [0]{0} read 0x100f8000 from pmpaddr8 (valid=0) Debug: 824 4456 riscv.c:1773 riscv_start_algorithm(): save pmpaddr9 Debug: 825 4461 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr953 on hart 0 Debug: 826 4465 riscv-013.c:802 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9 Debug: 827 4473 riscv-013.c:1510 register_read_direct(): {0} csr953 = 0x10a00000 Debug: 828 4478 riscv.c:3374 riscv_get_register_on_hart(): {0} csr953: 10a00000 Debug: 829 4481 riscv.c:3734 register_get(): [0]{0} read 0x10a00000 from pmpaddr9 (valid=0) Debug: 830 4487 riscv.c:1773 riscv_start_algorithm(): save pmpaddr10 Debug: 831 4491 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr954 on hart 0 Debug: 832 4495 riscv-013.c:802 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba Debug: 833 4504 riscv-013.c:1510 register_read_direct(): {0} csr954 = 0x14000000 Debug: 834 4508 riscv.c:3374 riscv_get_register_on_hart(): {0} csr954: 14000000 Debug: 835 4511 riscv.c:3734 register_get(): [0]{0} read 0x14000000 from pmpaddr10 (valid=0) Debug: 836 4517 riscv.c:1773 riscv_start_algorithm(): save pmpaddr11 Debug: 837 4522 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr955 on hart 0 Debug: 838 4527 riscv-013.c:802 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb Debug: 839 4536 riscv-013.c:1510 register_read_direct(): {0} csr955 = 0x14000800 Debug: 840 4539 riscv.c:3374 riscv_get_register_on_hart(): {0} csr955: 14000800 Debug: 841 4544 riscv.c:3734 register_get(): [0]{0} read 0x14000800 from pmpaddr11 (valid=0) Debug: 842 4548 riscv.c:1773 riscv_start_algorithm(): save pmpaddr12 Debug: 843 4552 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr956 on hart 0 Debug: 844 4557 riscv-013.c:802 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc Debug: 845 4566 riscv-013.c:1510 register_read_direct(): {0} csr956 = 0x18000000 Debug: 846 4569 riscv.c:3374 riscv_get_register_on_hart(): {0} csr956: 18000000 Debug: 847 4573 riscv.c:3734 register_get(): [0]{0} read 0x18000000 from pmpaddr12 (valid=0) Debug: 848 4578 riscv.c:1773 riscv_start_algorithm(): save pmpaddr13 Debug: 849 4582 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr957 on hart 0 Debug: 850 4586 riscv-013.c:802 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd Debug: 851 4597 riscv-013.c:1510 register_read_direct(): {0} csr957 = 0x18040000 Debug: 852 4600 riscv.c:3374 riscv_get_register_on_hart(): {0} csr957: 18040000 Debug: 853 4604 riscv.c:3734 register_get(): [0]{0} read 0x18040000 from pmpaddr13 (valid=0) Debug: 854 4608 riscv.c:1773 riscv_start_algorithm(): save pmpaddr14 Debug: 855 4612 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr958 on hart 0 Debug: 856 4617 riscv-013.c:802 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be Debug: 857 4629 riscv-013.c:1510 register_read_direct(): {0} csr958 = 0x3fffffff Debug: 858 4634 riscv.c:3374 riscv_get_register_on_hart(): {0} csr958: 3fffffff Debug: 859 4638 riscv.c:3734 register_get(): [0]{0} read 0x3fffffff from pmpaddr14 (valid=0) Debug: 860 4643 riscv.c:1773 riscv_start_algorithm(): save pmpaddr15 Debug: 861 4646 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr959 on hart 0 Debug: 862 4650 riscv-013.c:802 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf Debug: 863 4661 riscv-013.c:1510 register_read_direct(): {0} csr959 = 0x3fffffff Debug: 864 4665 riscv.c:3374 riscv_get_register_on_hart(): {0} csr959: 3fffffff Debug: 865 4669 riscv.c:3734 register_get(): [0]{0} read 0x3fffffff from pmpaddr15 (valid=0) Debug: 866 4675 riscv.c:1773 riscv_start_algorithm(): save tselect Debug: 867 4679 riscv-013.c:3715 riscv013_get_register(): [0] reading register tselect on hart 0 Debug: 868 4683 riscv-013.c:802 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0 Debug: 869 4694 riscv-013.c:1510 register_read_direct(): {0} tselect = 0x0 Debug: 870 4697 riscv.c:3374 riscv_get_register_on_hart(): {0} tselect: 0 Debug: 871 4702 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from tselect (valid=0) Debug: 872 4706 riscv.c:1773 riscv_start_algorithm(): save tdata1 Debug: 873 4710 riscv-013.c:3715 riscv013_get_register(): [0] reading register tdata1 on hart 0 Debug: 874 4714 riscv-013.c:802 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1 Debug: 875 4726 riscv-013.c:1510 register_read_direct(): {0} tdata1 = 0x23e00000 Debug: 876 4729 riscv.c:3374 riscv_get_register_on_hart(): {0} tdata1: 23e00000 Debug: 877 4735 riscv.c:3734 register_get(): [0]{0} read 0x23e00000 from tdata1 (valid=0) Debug: 878 4740 riscv.c:1773 riscv_start_algorithm(): save tdata2 Debug: 879 4744 riscv-013.c:3715 riscv013_get_register(): [0] reading register tdata2 on hart 0 Debug: 880 4749 riscv-013.c:802 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2 Debug: 881 4759 riscv-013.c:1510 register_read_direct(): {0} tdata2 = 0x0 Debug: 882 4764 riscv.c:3374 riscv_get_register_on_hart(): {0} tdata2: 0 Debug: 883 4768 riscv.c:3734 register_get(): [0]{0} read 0x00000000 from tdata2 (valid=0) Debug: 884 4772 riscv.c:1773 riscv_start_algorithm(): save dcsr Debug: 885 4775 riscv-013.c:3715 riscv013_get_register(): [0] reading register dcsr on hart 0 Debug: 886 4781 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 887 4795 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 888 4799 riscv.c:3374 riscv_get_register_on_hart(): {0} dcsr: 4000b0c3 Debug: 889 4802 riscv.c:3734 register_get(): [0]{0} read 0x4000b0c3 from dcsr (valid=1) Debug: 890 4806 riscv.c:1773 riscv_start_algorithm(): save dpc Debug: 891 4810 riscv-013.c:3715 riscv013_get_register(): [0] reading register dpc on hart 0 Debug: 892 4815 riscv-013.c:802 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 893 4823 riscv-013.c:1510 register_read_direct(): {0} dpc = 0x40380000 Debug: 894 4827 riscv.c:3374 riscv_get_register_on_hart(): {0} dpc: 40380000 Debug: 895 4831 riscv.c:3734 register_get(): [0]{0} read 0x40380000 from dpc (valid=1) Debug: 896 4835 riscv.c:1773 riscv_start_algorithm(): save dscratch0 Debug: 897 4839 riscv-013.c:3715 riscv013_get_register(): [0] reading register dscratch0 on hart 0 Debug: 898 4843 riscv-013.c:802 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2 Debug: 899 4853 riscv-013.c:1510 register_read_direct(): {0} dscratch0 = 0x600d0170 Debug: 900 4857 riscv.c:3374 riscv_get_register_on_hart(): {0} dscratch0: 600d0170 Debug: 901 4861 riscv.c:3734 register_get(): [0]{0} read 0x600d0170 from dscratch0 (valid=1) Debug: 902 4866 riscv.c:1773 riscv_start_algorithm(): save dscratch1 Debug: 903 4870 riscv-013.c:3715 riscv013_get_register(): [0] reading register csr1971 on hart 0 Debug: 904 4874 riscv-013.c:802 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3 Debug: 905 4882 riscv-013.c:1510 register_read_direct(): {0} csr1971 = 0x600d00c0 Debug: 906 4887 riscv.c:3374 riscv_get_register_on_hart(): {0} csr1971: 600d00c0 Debug: 907 4890 riscv.c:3734 register_get(): [0]{0} read 0x600d00c0 from dscratch1 (valid=0) Debug: 908 4895 riscv.c:1773 riscv_start_algorithm(): save priv Debug: 909 4899 riscv-013.c:3715 riscv013_get_register(): [0] reading register priv on hart 0 Debug: 910 4903 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 911 4912 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 912 4916 riscv.c:3374 riscv_get_register_on_hart(): {0} priv: 3 Debug: 913 4920 riscv.c:3734 register_get(): [0]{0} read 0x03 from priv (valid=0) Debug: 914 4923 riscv.c:1800 riscv_start_algorithm(): set sp Debug: 915 4927 riscv.c:3747 register_set(): [0]{0} write 0x3fc848a0 to sp (valid=1) Debug: 916 4932 riscv.c:3315 riscv_set_register_on_hart(): {0} sp <- 3fc848a0 Debug: 917 4936 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x3fc848a0 to register sp on hart 0 Debug: 918 4940 riscv-013.c:1320 register_write_direct(): {0} sp <- 0x3fc848a0 Debug: 919 4946 riscv-013.c:802 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002 Debug: 920 4957 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x3fc848a0 to sp valid=1 Debug: 921 4963 riscv.c:1800 riscv_start_algorithm(): set a7 Debug: 922 4966 riscv.c:3747 register_set(): [0]{0} write 0x403816e4 to a7 (valid=1) Debug: 923 4969 riscv.c:3315 riscv_set_register_on_hart(): {0} a7 <- 403816e4 Debug: 924 4973 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x403816e4 to register a7 on hart 0 Debug: 925 4979 riscv-013.c:1320 register_write_direct(): {0} a7 <- 0x403816e4 Debug: 926 4984 riscv-013.c:802 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011 Debug: 927 4993 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x403816e4 to a7 valid=1 Debug: 928 4997 riscv.c:1800 riscv_start_algorithm(): set a0 Debug: 929 5000 riscv.c:3747 register_set(): [0]{0} write 0x00000005 to a0 (valid=1) Debug: 930 5005 riscv.c:3315 riscv_set_register_on_hart(): {0} a0 <- 5 Debug: 931 5009 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x5 to register a0 on hart 0 Debug: 932 5013 riscv-013.c:1320 register_write_direct(): {0} a0 <- 0x5 Debug: 933 5017 riscv-013.c:802 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a Debug: 934 5027 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x5 to a0 valid=1 Debug: 935 5031 riscv.c:1800 riscv_start_algorithm(): set a1 Debug: 936 5034 riscv.c:3747 register_set(): [0]{0} write 0xffffffff to a1 (valid=1) Debug: 937 5039 riscv.c:3315 riscv_set_register_on_hart(): {0} a1 <- ffffffff Debug: 938 5043 riscv-013.c:3741 riscv013_set_register(): [0] writing 0xffffffff to register a1 on hart 0 Debug: 939 5048 riscv-013.c:1320 register_write_direct(): {0} a1 <- 0xffffffff Debug: 940 5052 riscv-013.c:802 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b Debug: 941 5061 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0xffffffff to a1 valid=1 Debug: 942 5066 riscv.c:1800 riscv_start_algorithm(): set a2 Debug: 943 5069 riscv.c:3747 register_set(): [0]{0} write 0x3fc848b8 to a2 (valid=1) Debug: 944 5073 riscv.c:3315 riscv_set_register_on_hart(): {0} a2 <- 3fc848b8 Debug: 945 5077 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x3fc848b8 to register a2 on hart 0 Debug: 946 5082 riscv-013.c:1320 register_write_direct(): {0} a2 <- 0x3fc848b8 Debug: 947 5087 riscv-013.c:802 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c Debug: 948 5095 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x3fc848b8 to a2 valid=1 Debug: 949 5100 riscv.c:1859 riscv_interrupts_disable(): Disabling Interrupts Debug: 950 5104 riscv.c:3358 riscv_get_register_on_hart(): {0} mstatus: 1800 (cached) Debug: 951 5108 riscv.c:3734 register_get(): [0]{0} read 0x00001800 from mstatus (valid=1) Debug: 952 5113 riscv.c:3747 register_set(): [0]{0} write 0x00001800 to mstatus (valid=1) Debug: 953 5119 riscv.c:3315 riscv_set_register_on_hart(): {0} mstatus <- 1800 Debug: 954 5123 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x1800 to register mstatus on hart 0 Debug: 955 5129 riscv-013.c:1320 register_write_direct(): {0} mstatus <- 0x1800 Debug: 956 5134 riscv-013.c:802 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300 Debug: 957 5145 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x1800 to mstatus valid=0 Debug: 958 5150 riscv.c:1832 riscv_start_algorithm(): resume at 0x40381de0 Debug: 959 5154 riscv.c:1382 riscv_resume(): handle_breakpoints=0 Debug: 960 5158 riscv.c:1309 resume_prep(): [0] Debug: 961 5161 riscv.c:3315 riscv_set_register_on_hart(): {0} pc <- 40381de0 Debug: 962 5165 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x40381de0 to register pc on hart 0 Debug: 963 5170 riscv-013.c:3748 riscv013_set_register(): [0] writing PC to DPC: 0x40381de0 Debug: 964 5175 riscv-013.c:1320 register_write_direct(): {0} dpc <- 0x40381de0 Debug: 965 5180 riscv-013.c:802 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1 Debug: 966 5189 riscv-013.c:802 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 967 5197 riscv-013.c:1510 register_read_direct(): {0} dpc = 0x40381de0 Debug: 968 5200 riscv-013.c:3752 riscv013_set_register(): [0] actual DPC written: 0x0000000040381de0 Debug: 969 5205 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x40381de0 to pc valid=0 Debug: 970 5210 riscv.c:1160 riscv_resume_prep_all_harts(): prep hart 0 Debug: 971 5215 log.c:428 gdb_timeout_warning(): keep_alive() was not invoked in the 1000 ms timelimit (2609 ms). This may cause trouble with GDB connections. Debug: 973 5222 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 974 5227 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100f @0 Debug: 975 5231 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 976 5236 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0xf @1 Debug: 977 5240 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 978 5244 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 979 5249 riscv-013.c:802 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 980 5257 riscv-013.c:802 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0 Debug: 981 5267 riscv-013.c:1510 register_read_direct(): {0} dcsr = 0x4000b0c3 Debug: 982 5270 riscv.c:3315 riscv_set_register_on_hart(): {0} dcsr <- 4000b0c3 Debug: 983 5274 riscv-013.c:3741 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr on hart 0 Debug: 984 5281 riscv-013.c:1320 register_write_direct(): {0} dcsr <- 0x4000b0c3 Debug: 985 5286 riscv-013.c:802 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0 Debug: 986 5295 riscv.c:3332 riscv_set_register_on_hart(): [esp32c3]{0} wrote 0x4000b0c3 to dcsr valid=0 Debug: 987 5301 riscv.c:1171 riscv_resume_prep_all_harts(): [0] mark as prepped Debug: 988 5304 riscv.c:1334 resume_prep(): [0] mark as prepped Debug: 989 5308 riscv.c:3070 riscv_resume_go_all_harts(): resuming hart 0 Debug: 990 5313 riscv-013.c:3817 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 991 5318 riscv-013.c:4445 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0) Debug: 992 5327 riscv.c:3209 riscv_invalidate_register_cache(): [0] Debug: 993 5328 target.c:1849 target_call_event_callbacks(): target event 2 (resumed) for core esp32c3 Debug: 994 5333 esp32c3.c:113 esp32c3_handle_target_event(): 2 Debug: 995 5338 esp_riscv.c:185 esp_riscv_handle_target_event(): 2 Debug: 996 5342 algorithm.c:246 algorithm_run(): Wait algorithm completion Error: 997 45347 riscv.c:1898 riscv_wait_algorithm(): Algorithm timed out after 40001 ms. Debug: 998 80679 riscv.c:1092 riscv_halt(): [0] halting all harts Debug: 999 80686 riscv.c:1024 halt_prep(): [esp32c3] prep hart, debug_reason=5 Debug: 1000 80700 riscv-013.c:3817 select_prepped_harts(): index=0, coreid=0, prepped=1 Debug: 1001 80704 riscv-013.c:3858 riscv013_halt_go(): halting hart 0 Debug: 1002 80712 riscv.c:3209 riscv_invalidate_register_cache(): [0] Debug: 1003 80715 target.c:1849 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3 Debug: 1004 80721 esp32c3.c:113 esp32c3_handle_target_event(): 0 Debug: 1005 80725 esp_riscv.c:185 esp_riscv_handle_target_event(): 0 Debug: 1006 80729 target.c:1849 target_call_event_callbacks(): target event 1 (halted) for core esp32c3 Debug: 1007 80734 target.c:4849 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action: esp32c3_wdt_disable

Debug: 1008 80743 command.c:146 script_debug(): command - command mode Debug: 1009 80746 command.c:146 script_debug(): command - mww 0x6001f064 0x50D83AA1 Debug: 1010 80749 log.c:428 gdb_timeout_warning(): keep_alive() was not invoked in the 1000 ms timelimit (75534 ms). This may cause trouble with GDB connections. Debug: 1013 80761 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f064 Debug: 1014 80768 command.c:146 script_debug(): command - mww 0x6001F048 0 Debug: 1016 80774 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x6001f048 Debug: 1017 80780 command.c:146 script_debug(): command - mww 0x60020064 0x50D83AA1 Debug: 1019 80787 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020064 Debug: 1020 80794 command.c:146 script_debug(): command - mww 0x60020048 0 Debug: 1022 80800 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60020048 Debug: 1023 80806 command.c:146 script_debug(): command - mww 0x600080a8 0x50D83AA1 Debug: 1025 80812 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080a8 Debug: 1026 80817 command.c:146 script_debug(): command - mww 0x60008090 0 Debug: 1028 80822 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x60008090 Debug: 1029 80829 command.c:146 script_debug(): command - mww 0x600080b0 0x8F1D312A Debug: 1031 80835 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080b0 Debug: 1032 80844 command.c:146 script_debug(): command - mww 0x600080ac 0x84B00000 Debug: 1034 80850 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x600080ac Debug: 1035 80855 esp32c3.c:113 esp32c3_handle_target_event(): 1 Debug: 1036 80860 esp_riscv.c:185 esp_riscv_handle_target_event(): 1 Debug: 1037 80864 riscv-013.c:3715 riscv013_get_register(): [0] reading register ra on hart 0 Debug: 1038 80868 riscv-013.c:802 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001 Debug: 1039 80878 riscv-013.c:1510 register_read_direct(): {0} ra = 0x0 Debug: 1040 80881 riscv.c:3374 riscv_get_register_on_hart(): {0} ra: 0 Error: 1041 80885 riscv.c:1918 riscv_wait_algorithm(): ra = 0x0 Debug: 1042 80889 riscv-013.c:3715 riscv013_get_register(): [0] reading register sp on hart 0 Debug: 1043 80894 riscv-013.c:802 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002 Debug: 1044 80903 riscv-013.c:1510 register_read_direct(): {0} sp = 0x3fc848a0 Debug: 1045 80906 riscv.c:3374 riscv_get_register_on_hart(): {0} sp: 3fc848a0 Error: 1046 80911 riscv.c:1918 riscv_wait_algorithm(): sp = 0x3fc848a0 Debug: 1047 80914 riscv-013.c:3715 riscv013_get_register(): [0] reading register gp on hart 0 Debug: 1048 80919 riscv-013.c:802 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003 Debug: 1049 80928 riscv-013.c:1510 register_read_direct(): {0} gp = 0x3fc8aa00 Debug: 1050 80932 riscv.c:3374 riscv_get_register_on_hart(): {0} gp: 3fc8aa00 Error: 1051 80936 riscv.c:1918 riscv_wait_algorithm(): gp = 0x3fc8aa00 Debug: 1052 80939 riscv-013.c:3715 riscv013_get_register(): [0] reading register tp on hart 0 Debug: 1053 80944 riscv-013.c:802 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004 Debug: 1054 80954 riscv-013.c:1510 register_read_direct(): {0} tp = 0x3fc890f0 Debug: 1055 80957 riscv.c:3374 riscv_get_register_on_hart(): {0} tp: 3fc890f0 Error: 1056 80960 riscv.c:1918 riscv_wait_algorithm(): tp = 0x3fc890f0 Debug: 1057 80965 riscv-013.c:3715 riscv013_get_register(): [0] reading register t0 on hart 0 Debug: 1058 80969 riscv-013.c:802 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005 Debug: 1059 80979 riscv-013.c:1510 register_read_direct(): {0} t0 = 0x80000000 Debug: 1060 80982 riscv.c:3374 riscv_get_register_on_hart(): {0} t0: 80000000 Error: 1061 80985 riscv.c:1918 riscv_wait_algorithm(): t0 = 0x80000000 Debug: 1062 80989 riscv-013.c:3715 riscv013_get_register(): [0] reading register t1 on hart 0 Debug: 1063 80994 riscv-013.c:802 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006 Debug: 1064 81003 riscv-013.c:1510 register_read_direct(): {0} t1 = 0x400510a0 Debug: 1065 81007 riscv.c:3374 riscv_get_register_on_hart(): {0} t1: 400510a0 Error: 1066 81011 riscv.c:1918 riscv_wait_algorithm(): t1 = 0x400510a0 Debug: 1067 81014 riscv-013.c:3715 riscv013_get_register(): [0] reading register t2 on hart 0 Debug: 1068 81018 riscv-013.c:802 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007 Debug: 1069 81029 riscv-013.c:1510 register_read_direct(): {0} t2 = 0x0 Debug: 1070 81033 riscv.c:3374 riscv_get_register_on_hart(): {0} t2: 0 Error: 1071 81037 riscv.c:1918 riscv_wait_algorithm(): t2 = 0x0 Debug: 1072 81040 riscv-013.c:3715 riscv013_get_register(): [0] reading register s0 on hart 0 Debug: 1073 81044 riscv-013.c:802 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1074 81054 riscv-013.c:1510 register_read_direct(): {0} s0 = 0x600d0170 Debug: 1075 81057 riscv.c:3374 riscv_get_register_on_hart(): {0} s0: 600d0170 Error: 1076 81061 riscv.c:1918 riscv_wait_algorithm(): s0 = 0x600d0170 Debug: 1077 81064 riscv-013.c:3715 riscv013_get_register(): [0] reading register s1 on hart 0 Debug: 1078 81070 riscv-013.c:802 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 1079 81078 riscv-013.c:1510 register_read_direct(): {0} s1 = 0x1 Debug: 1080 81083 riscv.c:3374 riscv_get_register_on_hart(): {0} s1: 1 Error: 1081 81086 riscv.c:1918 riscv_wait_algorithm(): s1 = 0x1 Debug: 1082 81089 riscv-013.c:3715 riscv013_get_register(): [0] reading register a0 on hart 0 Debug: 1083 81094 riscv-013.c:802 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a Debug: 1084 81104 riscv-013.c:1510 register_read_direct(): {0} a0 = 0x5 Debug: 1085 81108 riscv.c:3374 riscv_get_register_on_hart(): {0} a0: 5 Error: 1086 81113 riscv.c:1918 riscv_wait_algorithm(): a0 = 0x5 Debug: 1087 81117 riscv-013.c:3715 riscv013_get_register(): [0] reading register a1 on hart 0 Debug: 1088 81121 riscv-013.c:802 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b Debug: 1089 81130 riscv-013.c:1510 register_read_direct(): {0} a1 = 0xffffffff Debug: 1090 81133 riscv.c:3374 riscv_get_register_on_hart(): {0} a1: ffffffff Error: 1091 81137 riscv.c:1918 riscv_wait_algorithm(): a1 = 0xffffffff Debug: 1092 81140 riscv-013.c:3715 riscv013_get_register(): [0] reading register a2 on hart 0 Debug: 1093 81146 riscv-013.c:802 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c Debug: 1094 81155 riscv-013.c:1510 register_read_direct(): {0} a2 = 0x3fc848b8 Debug: 1095 81159 riscv.c:3374 riscv_get_register_on_hart(): {0} a2: 3fc848b8 Error: 1096 81163 riscv.c:1918 riscv_wait_algorithm(): a2 = 0x3fc848b8 Debug: 1097 81167 riscv-013.c:3715 riscv013_get_register(): [0] reading register a3 on hart 0 Debug: 1098 81173 riscv-013.c:802 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d Debug: 1099 81183 riscv-013.c:1510 register_read_direct(): {0} a3 = 0x4 Debug: 1100 81186 riscv.c:3374 riscv_get_register_on_hart(): {0} a3: 4 Error: 1101 81191 riscv.c:1918 riscv_wait_algorithm(): a3 = 0x4 Debug: 1102 81194 riscv-013.c:3715 riscv013_get_register(): [0] reading register a4 on hart 0 Debug: 1103 81198 riscv-013.c:802 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e Debug: 1104 81208 riscv-013.c:1510 register_read_direct(): {0} a4 = 0x600c4000 Debug: 1105 81211 riscv.c:3374 riscv_get_register_on_hart(): {0} a4: 600c4000 Error: 1106 81215 riscv.c:1918 riscv_wait_algorithm(): a4 = 0x600c4000 Debug: 1107 81219 riscv-013.c:3715 riscv013_get_register(): [0] reading register a5 on hart 0 Debug: 1108 81223 riscv-013.c:802 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f Debug: 1109 81232 riscv-013.c:1510 register_read_direct(): {0} a5 = 0x600c4000 Debug: 1110 81236 riscv.c:3374 riscv_get_register_on_hart(): {0} a5: 600c4000 Error: 1111 81240 riscv.c:1918 riscv_wait_algorithm(): a5 = 0x600c4000 Debug: 1112 81244 riscv-013.c:3715 riscv013_get_register(): [0] reading register a6 on hart 0 Debug: 1113 81250 riscv-013.c:802 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010 Debug: 1114 81259 riscv-013.c:1510 register_read_direct(): {0} a6 = 0x0 Debug: 1115 81262 riscv.c:3374 riscv_get_register_on_hart(): {0} a6: 0 Error: 1116 81267 riscv.c:1918 riscv_wait_algorithm(): a6 = 0x0 Debug: 1117 81270 riscv-013.c:3715 riscv013_get_register(): [0] reading register a7 on hart 0 Debug: 1118 81274 riscv-013.c:802 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011 Debug: 1119 81284 riscv-013.c:1510 register_read_direct(): {0} a7 = 0x403816e4 Debug: 1120 81287 riscv.c:3374 riscv_get_register_on_hart(): {0} a7: 403816e4 Error: 1121 81291 riscv.c:1918 riscv_wait_algorithm(): a7 = 0x403816e4 Debug: 1122 81295 riscv-013.c:3715 riscv013_get_register(): [0] reading register s2 on hart 0 Debug: 1123 81300 riscv-013.c:802 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012 Debug: 1124 81312 riscv-013.c:1510 register_read_direct(): {0} s2 = 0x0 Debug: 1125 81315 riscv.c:3374 riscv_get_register_on_hart(): {0} s2: 0 Error: 1126 81318 riscv.c:1918 riscv_wait_algorithm(): s2 = 0x0 Debug: 1127 81321 riscv-013.c:3715 riscv013_get_register(): [0] reading register s3 on hart 0 Debug: 1128 81327 riscv-013.c:802 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013 Debug: 1129 81337 riscv-013.c:1510 register_read_direct(): {0} s3 = 0x0 Debug: 1130 81341 riscv.c:3374 riscv_get_register_on_hart(): {0} s3: 0 Error: 1131 81344 riscv.c:1918 riscv_wait_algorithm(): s3 = 0x0 Debug: 1132 81347 riscv-013.c:3715 riscv013_get_register(): [0] reading register s4 on hart 0 Debug: 1133 81352 riscv-013.c:802 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014 Debug: 1134 81361 riscv-013.c:1510 register_read_direct(): {0} s4 = 0x0 Debug: 1135 81364 riscv.c:3374 riscv_get_register_on_hart(): {0} s4: 0 Error: 1136 81369 riscv.c:1918 riscv_wait_algorithm(): s4 = 0x0 Debug: 1137 81372 riscv-013.c:3715 riscv013_get_register(): [0] reading register s5 on hart 0 Debug: 1138 81377 riscv-013.c:802 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015 Debug: 1139 81386 riscv-013.c:1510 register_read_direct(): {0} s5 = 0x0 Debug: 1140 81389 riscv.c:3374 riscv_get_register_on_hart(): {0} s5: 0 Error: 1141 81394 riscv.c:1918 riscv_wait_algorithm(): s5 = 0x0 Debug: 1142 81397 riscv-013.c:3715 riscv013_get_register(): [0] reading register s6 on hart 0 Debug: 1143 81402 riscv-013.c:802 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016 Debug: 1144 81411 riscv-013.c:1510 register_read_direct(): {0} s6 = 0x0 Debug: 1145 81416 riscv.c:3374 riscv_get_register_on_hart(): {0} s6: 0 Error: 1146 81419 riscv.c:1918 riscv_wait_algorithm(): s6 = 0x0 Debug: 1147 81422 riscv-013.c:3715 riscv013_get_register(): [0] reading register s7 on hart 0 Debug: 1148 81427 riscv-013.c:802 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017 Debug: 1149 81436 riscv-013.c:1510 register_read_direct(): {0} s7 = 0x0 Debug: 1150 81439 riscv.c:3374 riscv_get_register_on_hart(): {0} s7: 0 Error: 1151 81442 riscv.c:1918 riscv_wait_algorithm(): s7 = 0x0 Debug: 1152 81447 riscv-013.c:3715 riscv013_get_register(): [0] reading register s8 on hart 0 Debug: 1153 81451 riscv-013.c:802 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018 Debug: 1154 81461 riscv-013.c:1510 register_read_direct(): {0} s8 = 0x0 Debug: 1155 81464 riscv.c:3374 riscv_get_register_on_hart(): {0} s8: 0 Error: 1156 81468 riscv.c:1918 riscv_wait_algorithm(): s8 = 0x0 Debug: 1157 81472 riscv-013.c:3715 riscv013_get_register(): [0] reading register s9 on hart 0 Debug: 1158 81478 riscv-013.c:802 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019 Debug: 1159 81488 riscv-013.c:1510 register_read_direct(): {0} s9 = 0x0 Debug: 1160 81493 riscv.c:3374 riscv_get_register_on_hart(): {0} s9: 0 Error: 1161 81497 riscv.c:1918 riscv_wait_algorithm(): s9 = 0x0 Debug: 1162 81500 riscv-013.c:3715 riscv013_get_register(): [0] reading register s10 on hart 0 Debug: 1163 81506 riscv-013.c:802 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a Debug: 1164 81517 riscv-013.c:1510 register_read_direct(): {0} s10 = 0x0 Debug: 1165 81522 riscv.c:3374 riscv_get_register_on_hart(): {0} s10: 0 Error: 1166 81525 riscv.c:1918 riscv_wait_algorithm(): s10 = 0x0 Debug: 1167 81528 riscv-013.c:3715 riscv013_get_register(): [0] reading register s11 on hart 0 Debug: 1168 81533 riscv-013.c:802 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b Debug: 1169 81546 riscv-013.c:1510 register_read_direct(): {0} s11 = 0x0 Debug: 1170 81551 riscv.c:3374 riscv_get_register_on_hart(): {0} s11: 0 Error: 1171 81554 riscv.c:1918 riscv_wait_algorithm(): s11 = 0x0 Debug: 1172 81557 riscv-013.c:3715 riscv013_get_register(): [0] reading register t3 on hart 0 Debug: 1173 81563 riscv-013.c:802 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c Debug: 1174 81573 riscv-013.c:1510 register_read_direct(): {0} t3 = 0x0 Debug: 1175 81577 riscv.c:3374 riscv_get_register_on_hart(): {0} t3: 0 Error: 1176 81581 riscv.c:1918 riscv_wait_algorithm(): t3 = 0x0 Debug: 1177 81584 riscv-013.c:3715 riscv013_get_register(): [0] reading register t4 on hart 0 Debug: 1178 81588 riscv-013.c:802 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d Debug: 1179 81599 riscv-013.c:1510 register_read_direct(): {0} t4 = 0x0 Debug: 1180 81602 riscv.c:3374 riscv_get_register_on_hart(): {0} t4: 0 Error: 1181 81605 riscv.c:1918 riscv_wait_algorithm(): t4 = 0x0 Debug: 1182 81608 riscv-013.c:3715 riscv013_get_register(): [0] reading register t5 on hart 0 Debug: 1183 81614 riscv-013.c:802 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e Debug: 1184 81623 riscv-013.c:1510 register_read_direct(): {0} t5 = 0x0 Debug: 1185 81626 riscv.c:3374 riscv_get_register_on_hart(): {0} t5: 0 Error: 1186 81630 riscv.c:1918 riscv_wait_algorithm(): t5 = 0x0 Debug: 1187 81633 riscv-013.c:3715 riscv013_get_register(): [0] reading register t6 on hart 0 Debug: 1188 81637 riscv-013.c:802 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f Debug: 1189 81647 riscv-013.c:1510 register_read_direct(): {0} t6 = 0x0 Debug: 1190 81650 riscv.c:3374 riscv_get_register_on_hart(): {0} t6: 0 Error: 1191 81653 riscv.c:1918 riscv_wait_algorithm(): t6 = 0x0 Debug: 1192 81657 riscv-013.c:3715 riscv013_get_register(): [0] reading register pc on hart 0 Debug: 1193 81663 riscv-013.c:802 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1 Debug: 1194 81672 riscv-013.c:1510 register_read_direct(): {0} dpc = 0x40380000 Debug: 1195 81676 riscv-013.c:3723 riscv013_get_register(): [0] read PC from DPC: 0x40380000 Debug: 1196 81681 riscv.c:3374 riscv_get_register_on_hart(): {0} pc: 40380000 Error: 1197 81684 riscv.c:1918 riscv_wait_algorithm(): pc = 0x40380000 Debug: 1198 81689 riscv-013.c:3715 riscv013_get_register(): [0] reading register mstatus on hart 0 Debug: 1199 81695 riscv-013.c:802 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300 Debug: 1200 81706 riscv-013.c:1510 register_read_direct(): {0} mstatus = 0x1800 Debug: 1201 81710 riscv.c:3374 riscv_get_register_on_hart(): {0} mstatus: 1800 Error: 1202 81713 riscv.c:1918 riscv_wait_algorithm(): mstatus = 0x1800 Debug: 1203 81716 riscv-013.c:3715 riscv013_get_register(): [0] reading register mepc on hart 0 Debug: 1204 81722 riscv-013.c:802 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341 Debug: 1205 81733 riscv-013.c:1510 register_read_direct(): {0} mepc = 0x40380000 Debug: 1206 81736 riscv.c:3374 riscv_get_register_on_hart(): {0} mepc: 40380000 Error: 1207 81740 riscv.c:1918 riscv_wait_algorithm(): mepc = 0x40380000 Debug: 1208 81745 riscv-013.c:3715 riscv013_get_register(): [0] reading register mcause on hart 0 Debug: 1209 81750 riscv-013.c:802 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342 Debug: 1210 81759 riscv-013.c:1510 register_read_direct(): {0} mcause = 0x2 Debug: 1211 81762 riscv.c:3374 riscv_get_register_on_hart(): {0} mcause: 2 Error: 1212 81767 riscv.c:1918 riscv_wait_algorithm(): mcause = 0x2 Error: 1213 81770 algorithm.c:253 algorithm_run(): Failed to wait algorithm (-302)! Error: 1214 81773 algorithm.c:271 algorithm_run(): Algorithm run failed (-302)! Debug: 1215 81780 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc848b8 Debug: 1216 81786 log.c:428 gdb_timeout_warning(): keep_alive() was not invoked in the 1000 ms timelimit (1037 ms). This may cause trouble with GDB connections. Debug: 1218 81795 target.c:2185 target_free_working_area_restore(): freed 28 bytes of working area at address 0x3fc848b8 Debug: 1219 81801 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1220 81805 target.c:1964 print_wa_layout(): b 0x3fc843a4-0x3fc848b7 (1300 bytes) Debug: 1221 81811 target.c:1964 print_wa_layout(): 0x3fc848b8-0x3fca3fff (128840 bytes) Debug: 1222 81817 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381de0 Debug: 1223 81823 target.c:2185 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381de0 Debug: 1224 81830 target.c:1964 print_wa_layout(): b 0x40380000-0x40381ddf (7648 bytes) Debug: 1225 81834 target.c:1964 print_wa_layout(): 0x40381de0-0x40383fff (8736 bytes) Debug: 1226 81839 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc843a4 Debug: 1227 81846 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84424 Debug: 1228 81851 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc844a4 Debug: 1229 81859 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84524 Debug: 1230 81865 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc845a4 Debug: 1231 81872 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84624 Debug: 1232 81878 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc846a4 Debug: 1233 81886 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84724 Debug: 1234 81894 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc847a4 Debug: 1235 81900 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84824 Debug: 1236 81906 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc848a4 Debug: 1237 81911 target.c:2185 target_free_working_area_restore(): freed 1300 bytes of working area at address 0x3fc843a4 Debug: 1238 81918 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1239 81922 target.c:1964 print_wa_layout(): 0x3fc843a4-0x3fca3fff (130140 bytes) Debug: 1240 81928 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 1241 81935 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 1242 81941 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 1243 81948 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 1244 81955 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 1245 81964 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 1246 81971 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 1247 81979 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 1248 81985 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 1249 81991 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 1250 81998 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 1251 82006 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 1252 82013 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 1253 82020 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 1254 82029 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 1255 82036 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 1256 82044 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 1257 82051 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 1258 82059 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 1259 82067 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 1260 82075 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 1261 82081 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 1262 82088 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 1263 82095 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 1264 82103 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 1265 82109 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 1266 82116 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 1267 82123 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 1268 82131 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 1269 82137 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 1270 82144 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 1271 82150 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 1272 82155 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 1273 82163 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 1274 82169 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 1275 82176 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 1276 82183 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 1277 82192 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 1278 82200 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 1279 82208 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 1280 82215 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 1281 82223 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 1282 82229 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 1283 82237 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 1284 82244 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 1285 82250 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 1286 82257 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 1287 82265 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 1288 82271 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 1289 82277 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 1290 82284 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 1292 82290 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 1293 82297 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 1294 82303 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 1295 82309 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 1296 82315 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 1297 82321 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 1298 82328 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 1299 82336 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 1300 82344 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 1301 82349 target.c:2185 target_free_working_area_restore(): freed 7648 bytes of working area at address 0x40380000 Debug: 1302 82356 target.c:1964 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes) Debug: 1303 82361 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 1304 82367 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 1305 82374 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 1306 82382 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 1307 82389 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 1308 82396 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84280 Debug: 1309 82403 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84300 Debug: 1310 82409 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84380 Debug: 1311 82414 target.c:2185 target_free_working_area_restore(): freed 932 bytes of working area at address 0x3fc84000 Debug: 1312 82420 target.c:1964 print_wa_layout(): 0x3fc84000-0x3fca3fff (131072 bytes) Error: 1313 82426 esp_flash.c:378 esp_flash_get_mappings(): Failed to run flasher stub (-302)! Warn : 1314 82430 esp_flash.c:941 esp_flash_probe(): Failed to get flash mappings (-302)! Debug: 1315 82434 esp_flash.c:242 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 1316 82438 algorithm.c:339 algorithm_load_func_image(): stub: base 0x0, start 0x403816e4, 2 sections Debug: 1317 82443 algorithm.c:346 algorithm_load_func_image(): addr 0x00000000, sz 7648, flags 1 Debug: 1318 82449 target.c:2097 alloc_working_area_try_do(): allocated new working area of 7648 bytes at address 0x40380000 Debug: 1319 82455 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:1912 start address: 0x40380000 Debug: 1320 82463 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380000 Debug: 1321 82470 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380080 Debug: 1322 82477 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380100 Debug: 1323 82483 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380180 Debug: 1324 82488 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380200 Debug: 1325 82495 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380280 Debug: 1326 82501 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380300 Debug: 1327 82508 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380380 Debug: 1328 82514 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380400 Debug: 1329 82519 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380480 Debug: 1330 82526 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380500 Debug: 1331 82532 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380580 Debug: 1332 82539 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380600 Debug: 1333 82545 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380680 Debug: 1334 82552 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380700 Debug: 1335 82559 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380780 Debug: 1336 82566 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380800 Debug: 1337 82572 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380880 Debug: 1338 82579 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380900 Debug: 1339 82586 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380980 Debug: 1340 82592 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380a00 Debug: 1341 82599 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380a80 Debug: 1342 82606 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380b00 Debug: 1343 82612 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380b80 Debug: 1344 82618 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380c00 Debug: 1345 82623 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380c80 Debug: 1346 82630 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380d00 Debug: 1347 82637 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380d80 Debug: 1348 82646 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380e00 Debug: 1349 82652 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380e80 Debug: 1350 82660 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380f00 Debug: 1351 82673 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380f80 Debug: 1352 82680 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381000 Debug: 1353 82687 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381080 Debug: 1354 82694 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381100 Debug: 1355 82701 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381180 Debug: 1356 82708 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381200 Debug: 1357 82714 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381280 Debug: 1358 82727 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381300 Debug: 1359 82735 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381380 Debug: 1360 82740 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381400 Debug: 1361 82746 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381480 Debug: 1362 82752 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381500 Debug: 1363 82758 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381580 Debug: 1364 82764 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381600 Debug: 1365 82770 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381680 Debug: 1366 82776 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381700 Debug: 1367 82782 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381780 Debug: 1368 82789 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381800 Debug: 1370 82798 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381880 Debug: 1371 82805 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381900 Debug: 1372 82812 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381980 Debug: 1373 82818 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381a00 Debug: 1374 82824 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381a80 Debug: 1375 82830 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381b00 Debug: 1376 82836 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381b80 Debug: 1377 82842 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381c00 Debug: 1378 82848 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381c80 Debug: 1379 82854 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381d00 Debug: 1380 82860 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381d80 Debug: 1381 82867 target.c:1964 print_wa_layout(): b* 0x40380000-0x40381ddf (7648 bytes) Debug: 1382 82873 target.c:1964 print_wa_layout(): 0x40381de0-0x40383fff (8736 bytes) Debug: 1383 82877 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380000 Debug: 1384 82883 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 1385 82890 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 1386 82897 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 1387 82905 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 1388 82912 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380200 Debug: 1389 82918 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 1390 82927 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 1391 82935 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 1392 82941 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 1393 82949 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380400 Debug: 1394 82954 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 1395 82961 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 1396 82969 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 1397 82978 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 1398 82984 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380600 Debug: 1399 82990 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 1400 82997 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 1401 83003 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 1402 83010 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 1403 83018 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380800 Debug: 1404 83024 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 1405 83031 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 1406 83038 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 1407 83045 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 1408 83052 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380a00 Debug: 1409 83057 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 1410 83063 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 1411 83070 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 1412 83079 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 1413 83086 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380c00 Debug: 1414 83092 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 1415 83100 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 1416 83106 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 1417 83114 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 1418 83121 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380e00 Debug: 1419 83129 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 1420 83136 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 1421 83143 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 1422 83150 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 1423 83159 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381000 Debug: 1424 83166 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 1425 83174 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 1426 83181 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 1427 83187 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 1428 83194 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381200 Debug: 1429 83199 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 1430 83206 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 1431 83213 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 1432 83221 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 1433 83228 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381400 Debug: 1434 83234 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 1435 83240 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 1436 83246 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 1437 83254 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 1438 83260 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381600 Debug: 1439 83266 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 1440 83273 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 1441 83281 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 1442 83287 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 1443 83294 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381800 Debug: 1444 83299 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 1446 83306 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 1447 83313 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 1448 83321 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 1449 83330 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381a00 Debug: 1450 83337 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 1451 83345 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 1452 83352 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 1453 83360 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 1454 83367 target.c:2445 target_write_buffer(): writing buffer of 480 byte at 0x40381c00 Debug: 1455 83373 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 1456 83379 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 1457 83385 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 1458 83393 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 1459 83400 algorithm.c:346 algorithm_load_func_image(): addr 0x00000000, sz 637, flags 0 Debug: 1460 83404 algorithm.c:376 algorithm_load_func_image(): DATA sec size 637 -> 640 Debug: 1461 83409 algorithm.c:379 algorithm_load_func_image(): BSS sec size 289 -> 292 Debug: 1462 83412 target.c:2097 alloc_working_area_try_do(): allocated new working area of 932 bytes at address 0x3fc84000 Debug: 1463 83419 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:233 start address: 0x3fc84000 Debug: 1464 83427 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84000 Debug: 1465 83435 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84080 Debug: 1466 83440 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84100 Debug: 1467 83447 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84180 Debug: 1468 83454 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84200 Debug: 1469 83461 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84280 Debug: 1470 83468 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84300 Debug: 1471 83476 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84380 Debug: 1472 83482 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1473 83487 target.c:1964 print_wa_layout(): 0x3fc843a4-0x3fca3fff (130140 bytes) Debug: 1474 83493 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000 Debug: 1475 83500 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 1476 83506 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 1477 83513 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 1478 83519 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 1479 83526 target.c:2445 target_write_buffer(): writing buffer of 125 byte at 0x3fc84200 Debug: 1480 83531 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 1481 83539 riscv-013.c:3447 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc8427c Debug: 1482 83543 riscv-013.c:802 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1483 83552 riscv-013.c:1510 register_read_direct(): {0} s0 = 0x600d0170 Debug: 1484 83556 riscv-013.c:802 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 1485 83565 riscv-013.c:1510 register_read_direct(): {0} s1 = 0x1 Debug: 1486 83568 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x00940023) Debug: 1487 83573 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x00140413) Debug: 1488 83578 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1489 83584 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1490 83589 riscv-013.c:3504 write_memory_progbuf(): writing until final address 0x000000003fc8427d Debug: 1491 83595 riscv-013.c:3507 write_memory_progbuf(): transferring burst starting at address 0x000000003fc8427c Debug: 1492 83602 riscv-013.c:1320 register_write_direct(): {0} s0 <- 0x3fc8427c Debug: 1493 83607 riscv-013.c:802 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 1494 83617 riscv-013.c:802 execute_abstract_command(): command=0x271009; access register, size=32, postexec=1, transfer=1, write=1, regno=0x1009 Debug: 1495 83628 batch.c:81 riscv_batch_run(): Ignoring empty batch. Debug: 1496 83632 riscv-013.c:3587 write_memory_progbuf(): successful (partial?) memory write Debug: 1497 83636 riscv-013.c:1320 register_write_direct(): {0} s1 <- 0x1 Debug: 1498 83641 riscv-013.c:802 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 1499 83651 riscv-013.c:1320 register_write_direct(): {0} s0 <- 0x600d0170 Debug: 1500 83655 riscv-013.c:802 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 1501 83665 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 1502 83670 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 1503 83675 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1504 83679 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1505 83683 riscv-013.c:802 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 1506 83694 target.c:2097 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3fc843a4 Debug: 1507 83700 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:256 start address: 0x3fc843a4 Debug: 1508 83710 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc843a4 Debug: 1509 83715 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84424 Debug: 1510 83723 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc844a4 Debug: 1511 83729 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84524 Debug: 1512 83735 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc845a4 Debug: 1513 83741 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84624 Debug: 1514 83748 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc846a4 Debug: 1515 83755 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84724 Debug: 1516 83763 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1517 83767 target.c:1964 print_wa_layout(): b 0x3fc843a4-0x3fc847a3 (1024 bytes) Debug: 1518 83771 target.c:1964 print_wa_layout(): 0x3fc847a4-0x3fca3fff (129116 bytes) Debug: 1519 83775 target.c:2097 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381de0 Debug: 1520 83782 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:1 start address: 0x40381de0 Debug: 1521 83790 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381de0 Debug: 1522 83797 target.c:1964 print_wa_layout(): b 0x40380000-0x40381ddf (7648 bytes) Debug: 1523 83801 target.c:1964 print_wa_layout(): b 0x40381de0-0x40381de3 (4 bytes) Debug: 1524 83805 target.c:1964 print_wa_layout(): 0x40381de4-0x40383fff (8732 bytes) Debug: 1525 83811 target.c:2445 target_write_buffer(): writing buffer of 4 byte at 0x40381de0 Debug: 1526 83816 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381de0 Debug: 1528 83823 algorithm.c:462 algorithm_load_func_image(): Stub loaded in 1385.15 ms Debug: 1529 83828 riscv_algorithm.c:53 riscv_algo_regs_init_start(): Check stack addr 0x3fc847a4 Debug: 1530 83832 riscv_algorithm.c:56 riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc847a0 Debug: 1531 83836 riscv_algorithm.c:96 riscv_algo_init(): Set arg[0] = 4 (a0) Debug: 1532 83841 algorithm.c:224 algorithm_run(): Algorithm start @ 0x40381de0, stack 1024 bytes @ 0x3fc847a4 Error: 1533 83846 target.c:907 target_start_algorithm(): Target is already running an algorithm Error: 1534 83851 algorithm.c:231 algorithm_run(): Failed to start algorithm (-4)! Debug: 1535 83857 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381de0 Debug: 1536 83864 target.c:2185 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381de0 Debug: 1537 83871 target.c:1964 print_wa_layout(): b 0x40380000-0x40381ddf (7648 bytes) Debug: 1538 83875 target.c:1964 print_wa_layout(): 0x40381de0-0x40383fff (8736 bytes) Debug: 1539 83881 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc843a4 Debug: 1540 83888 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84424 Debug: 1541 83895 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc844a4 Debug: 1542 83902 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84524 Debug: 1543 83909 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc845a4 Debug: 1544 83917 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84624 Debug: 1545 83923 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc846a4 Debug: 1546 83930 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84724 Debug: 1547 83937 target.c:2185 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3fc843a4 Debug: 1548 83946 target.c:1964 print_wa_layout(): b* 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1549 83949 target.c:1964 print_wa_layout(): 0x3fc843a4-0x3fca3fff (130140 bytes) Debug: 1550 83955 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 1551 83962 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 1552 83969 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 1553 83978 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 1554 83985 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 1555 83994 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 1556 84001 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 1557 84009 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 1558 84015 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 1559 84022 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 1560 84028 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 1561 84035 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 1562 84044 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 1563 84052 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 1564 84059 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 1565 84065 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 1566 84071 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 1567 84077 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 1568 84084 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 1569 84090 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 1570 84097 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 1571 84103 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 1572 84109 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 1573 84116 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 1574 84122 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 1575 84130 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 1576 84136 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 1577 84143 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 1578 84149 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 1579 84155 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 1580 84162 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 1581 84168 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 1582 84176 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 1583 84184 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 1584 84191 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 1585 84199 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 1586 84207 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 1587 84213 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 1588 84220 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 1589 84227 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 1590 84236 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 1591 84244 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 1592 84252 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 1593 84258 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 1594 84265 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 1595 84272 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 1596 84280 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 1597 84286 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 1598 84293 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 1599 84299 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 1600 84304 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 1601 84312 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 1602 84318 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 1604 84325 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 1605 84331 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 1606 84338 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 1607 84345 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 1608 84352 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 1609 84360 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 1610 84366 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 1611 84372 target.c:2185 target_free_working_area_restore(): freed 7648 bytes of working area at address 0x40380000 Debug: 1612 84379 target.c:1964 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes) Debug: 1613 84385 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 1614 84393 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 1615 84403 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 1616 84409 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 1617 84416 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 1618 84423 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84280 Debug: 1619 84432 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84300 Debug: 1620 84438 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84380 Debug: 1621 84443 target.c:2185 target_free_working_area_restore(): freed 932 bytes of working area at address 0x3fc84000 Debug: 1622 84450 target.c:1964 print_wa_layout(): 0x3fc84000-0x3fca3fff (131072 bytes) Error: 1623 84454 esp_flash.c:340 esp_flash_get_size(): Failed to run flasher stub (-4)! Debug: 1624 84458 esp_flash.c:242 esp_flasher_algorithm_init(): base=00000000 set=0 Debug: 1625 84463 algorithm.c:339 algorithm_load_func_image(): stub: base 0x0, start 0x403816e4, 2 sections Debug: 1626 84467 algorithm.c:346 algorithm_load_func_image(): addr 0x00000000, sz 7648, flags 1 Debug: 1627 84472 target.c:2097 alloc_working_area_try_do(): allocated new working area of 7648 bytes at address 0x40380000 Debug: 1628 84480 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:1912 start address: 0x40380000 Debug: 1629 84487 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380000 Debug: 1630 84494 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380080 Debug: 1631 84500 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380100 Debug: 1632 84506 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380180 Debug: 1633 84513 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380200 Debug: 1634 84520 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380280 Debug: 1635 84527 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380300 Debug: 1636 84532 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380380 Debug: 1637 84539 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380400 Debug: 1638 84545 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380480 Debug: 1639 84551 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380500 Debug: 1640 84557 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380580 Debug: 1641 84563 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380600 Debug: 1642 84569 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380680 Debug: 1643 84575 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380700 Debug: 1644 84582 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380780 Debug: 1645 84588 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380800 Debug: 1646 84593 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380880 Debug: 1647 84600 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380900 Debug: 1648 84606 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380980 Debug: 1649 84612 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380a00 Debug: 1650 84618 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380a80 Debug: 1651 84623 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380b00 Debug: 1652 84630 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380b80 Debug: 1653 84637 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380c00 Debug: 1654 84645 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380c80 Debug: 1655 84651 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380d00 Debug: 1656 84658 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380d80 Debug: 1657 84666 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380e00 Debug: 1658 84676 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380e80 Debug: 1659 84683 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380f00 Debug: 1660 84690 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40380f80 Debug: 1661 84698 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381000 Debug: 1662 84705 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381080 Debug: 1663 84711 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381100 Debug: 1664 84718 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381180 Debug: 1665 84723 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381200 Debug: 1666 84729 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381280 Debug: 1667 84736 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381300 Debug: 1668 84741 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381380 Debug: 1669 84749 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381400 Debug: 1670 84754 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381480 Debug: 1671 84760 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381500 Debug: 1672 84767 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381580 Debug: 1673 84772 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381600 Debug: 1674 84778 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381680 Debug: 1675 84784 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381700 Debug: 1676 84790 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381780 Debug: 1677 84797 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381800 Debug: 1678 84803 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381880 Debug: 1679 84809 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381900 Debug: 1680 84815 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381980 Debug: 1681 84820 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381a00 Debug: 1683 84827 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381a80 Debug: 1684 84833 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381b00 Debug: 1685 84839 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381b80 Debug: 1686 84845 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381c00 Debug: 1687 84851 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381c80 Debug: 1688 84858 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381d00 Debug: 1689 84864 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381d80 Debug: 1690 84870 target.c:1964 print_wa_layout(): b* 0x40380000-0x40381ddf (7648 bytes) Debug: 1691 84874 target.c:1964 print_wa_layout(): 0x40381de0-0x40383fff (8736 bytes) Debug: 1692 84879 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380000 Debug: 1693 84886 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 1694 84894 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 1695 84902 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 1696 84908 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 1697 84916 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380200 Debug: 1698 84922 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 1699 84930 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 1700 84936 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 1701 84941 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 1702 84949 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380400 Debug: 1703 84954 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 1704 84963 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 1705 84970 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 1706 84977 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 1707 84984 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380600 Debug: 1708 84992 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 1709 84998 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 1710 85007 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 1711 85014 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 1712 85021 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380800 Debug: 1713 85026 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 1714 85034 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 1715 85042 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 1716 85052 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 1717 85058 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380a00 Debug: 1718 85063 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 1719 85070 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 1720 85076 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 1721 85083 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 1722 85091 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380c00 Debug: 1723 85097 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 1724 85103 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 1725 85110 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 1726 85116 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 1727 85122 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40380e00 Debug: 1728 85128 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 1729 85136 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 1730 85145 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 1731 85151 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 1732 85159 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381000 Debug: 1733 85164 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 1734 85171 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 1735 85178 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 1736 85185 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 1737 85193 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381200 Debug: 1738 85200 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 1739 85209 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 1740 85218 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 1741 85224 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 1742 85233 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381400 Debug: 1743 85239 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 1744 85248 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 1745 85256 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 1746 85264 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 1747 85270 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381600 Debug: 1748 85276 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 1749 85283 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 1750 85289 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 1751 85296 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 1752 85304 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381800 Debug: 1753 85311 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 1754 85318 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 1755 85327 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 1757 85335 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 1758 85343 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x40381a00 Debug: 1759 85348 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 1760 85355 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 1761 85362 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 1762 85368 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 1763 85375 target.c:2445 target_write_buffer(): writing buffer of 480 byte at 0x40381c00 Debug: 1764 85381 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 1765 85388 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 1766 85395 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 1767 85404 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 1768 85410 algorithm.c:346 algorithm_load_func_image(): addr 0x00000000, sz 637, flags 0 Debug: 1769 85416 algorithm.c:376 algorithm_load_func_image(): DATA sec size 637 -> 640 Debug: 1770 85420 algorithm.c:379 algorithm_load_func_image(): BSS sec size 289 -> 292 Debug: 1771 85424 target.c:2097 alloc_working_area_try_do(): allocated new working area of 932 bytes at address 0x3fc84000 Debug: 1772 85431 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:233 start address: 0x3fc84000 Debug: 1773 85438 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84000 Debug: 1774 85446 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84080 Debug: 1775 85452 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84100 Debug: 1776 85458 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84180 Debug: 1777 85464 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84200 Debug: 1778 85470 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84280 Debug: 1779 85477 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84300 Debug: 1780 85482 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84380 Debug: 1781 85489 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1782 85494 target.c:1964 print_wa_layout(): 0x3fc843a4-0x3fca3fff (130140 bytes) Debug: 1783 85498 target.c:2445 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000 Debug: 1784 85504 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 1785 85511 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 1786 85517 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 1787 85524 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 1788 85530 target.c:2445 target_write_buffer(): writing buffer of 125 byte at 0x3fc84200 Debug: 1789 85537 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 1790 85543 riscv-013.c:3447 write_memory_progbuf(): writing 1 words of 1 bytes to 0x3fc8427c Debug: 1791 85549 riscv-013.c:802 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008 Debug: 1792 85559 riscv-013.c:1510 register_read_direct(): {0} s0 = 0x600d0170 Debug: 1793 85562 riscv-013.c:802 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009 Debug: 1794 85572 riscv-013.c:1510 register_read_direct(): {0} s1 = 0x1 Debug: 1795 85575 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x00940023) Debug: 1796 85580 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x00140413) Debug: 1797 85586 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1798 85589 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1799 85594 riscv-013.c:3504 write_memory_progbuf(): writing until final address 0x000000003fc8427d Debug: 1800 85599 riscv-013.c:3507 write_memory_progbuf(): transferring burst starting at address 0x000000003fc8427c Debug: 1801 85604 riscv-013.c:1320 register_write_direct(): {0} s0 <- 0x3fc8427c Debug: 1802 85609 riscv-013.c:802 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 1803 85620 riscv-013.c:802 execute_abstract_command(): command=0x271009; access register, size=32, postexec=1, transfer=1, write=1, regno=0x1009 Debug: 1804 85629 batch.c:81 riscv_batch_run(): Ignoring empty batch. Debug: 1805 85633 riscv-013.c:3587 write_memory_progbuf(): successful (partial?) memory write Debug: 1806 85639 riscv-013.c:1320 register_write_direct(): {0} s1 <- 0x1 Debug: 1807 85645 riscv-013.c:802 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009 Debug: 1808 85655 riscv-013.c:1320 register_write_direct(): {0} s0 <- 0x600d0170 Debug: 1809 85661 riscv-013.c:802 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008 Debug: 1810 85669 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f) Debug: 1811 85676 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f) Debug: 1812 85681 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073) Debug: 1813 85687 riscv-013.c:4011 riscv013_write_debug_buffer(): cache hit for 0x100073 @2 Debug: 1814 85692 riscv-013.c:802 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000 Debug: 1815 85701 target.c:2097 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3fc843a4 Debug: 1816 85708 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:256 start address: 0x3fc843a4 Debug: 1817 85717 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc843a4 Debug: 1818 85723 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84424 Debug: 1819 85730 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc844a4 Debug: 1820 85737 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84524 Debug: 1821 85745 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc845a4 Debug: 1822 85751 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84624 Debug: 1823 85757 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc846a4 Debug: 1824 85763 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x3fc84724 Debug: 1825 85769 target.c:1964 print_wa_layout(): b 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1826 85772 target.c:1964 print_wa_layout(): b 0x3fc843a4-0x3fc847a3 (1024 bytes) Debug: 1827 85777 target.c:1964 print_wa_layout(): 0x3fc847a4-0x3fca3fff (129116 bytes) Debug: 1828 85781 target.c:2097 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381de0 Debug: 1829 85787 riscv-013.c:2529 read_memory_bus_v1(): System Bus Access: size: 4 count:1 start address: 0x40381de0 Debug: 1830 85796 riscv-013.c:2546 read_memory_bus_v1(): reading burst starting at address 0x40381de0 Debug: 1831 85801 target.c:1964 print_wa_layout(): b 0x40380000-0x40381ddf (7648 bytes) Debug: 1832 85805 target.c:1964 print_wa_layout(): b 0x40381de0-0x40381de3 (4 bytes) Debug: 1833 85809 target.c:1964 print_wa_layout(): 0x40381de4-0x40383fff (8732 bytes) Debug: 1834 85813 target.c:2445 target_write_buffer(): writing buffer of 4 byte at 0x40381de0 Debug: 1835 85819 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381de0 Debug: 1836 85826 algorithm.c:462 algorithm_load_func_image(): Stub loaded in 1363.71 ms Debug: 1837 85830 riscv_algorithm.c:53 riscv_algo_regs_init_start(): Check stack addr 0x3fc847a4 Debug: 1838 85834 riscv_algorithm.c:56 riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc847a0 Debug: 1839 85840 riscv_algorithm.c:96 riscv_algo_init(): Set arg[0] = 4 (a0) Debug: 1840 85844 algorithm.c:224 algorithm_run(): Algorithm start @ 0x40381de0, stack 1024 bytes @ 0x3fc847a4 Error: 1841 85849 target.c:907 target_start_algorithm(): Target is already running an algorithm Error: 1842 85854 algorithm.c:231 algorithm_run(): Failed to start algorithm (-4)! Debug: 1843 85860 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381de0 Debug: 1845 85867 target.c:2185 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381de0 Debug: 1846 85874 target.c:1964 print_wa_layout(): b 0x40380000-0x40381ddf (7648 bytes) Debug: 1847 85879 target.c:1964 print_wa_layout(): 0x40381de0-0x40383fff (8736 bytes) Debug: 1848 85886 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc843a4 Debug: 1849 85895 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84424 Debug: 1850 85902 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc844a4 Debug: 1851 85910 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84524 Debug: 1852 85919 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc845a4 Debug: 1853 85926 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84624 Debug: 1854 85934 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc846a4 Debug: 1855 85940 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84724 Debug: 1856 85948 target.c:2185 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3fc843a4 Debug: 1857 85953 target.c:1964 print_wa_layout(): b* 0x3fc84000-0x3fc843a3 (932 bytes) Debug: 1858 85957 target.c:1964 print_wa_layout(): 0x3fc843a4-0x3fca3fff (130140 bytes) Debug: 1859 85964 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380000 Debug: 1860 85970 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380080 Debug: 1861 85977 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380100 Debug: 1862 85983 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380180 Debug: 1863 85990 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380200 Debug: 1864 85996 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380280 Debug: 1865 86004 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380300 Debug: 1866 86010 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380380 Debug: 1867 86016 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380400 Debug: 1868 86023 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380480 Debug: 1869 86029 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380500 Debug: 1870 86037 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380580 Debug: 1871 86045 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380600 Debug: 1872 86051 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380680 Debug: 1873 86057 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380700 Debug: 1874 86063 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380780 Debug: 1875 86070 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380800 Debug: 1876 86076 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380880 Debug: 1877 86082 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380900 Debug: 1878 86088 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380980 Debug: 1879 86094 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a00 Debug: 1880 86102 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380a80 Debug: 1881 86110 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b00 Debug: 1882 86117 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380b80 Debug: 1883 86123 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c00 Debug: 1884 86130 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380c80 Debug: 1885 86137 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d00 Debug: 1886 86145 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380d80 Debug: 1887 86151 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e00 Debug: 1888 86157 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380e80 Debug: 1889 86163 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f00 Debug: 1890 86169 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40380f80 Debug: 1891 86176 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381000 Debug: 1892 86182 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381080 Debug: 1893 86189 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381100 Debug: 1894 86196 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381180 Debug: 1895 86203 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381200 Debug: 1896 86209 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381280 Debug: 1897 86214 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381300 Debug: 1898 86222 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381380 Debug: 1899 86228 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381400 Debug: 1900 86235 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381480 Debug: 1901 86241 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381500 Debug: 1902 86247 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381580 Debug: 1903 86253 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381600 Debug: 1904 86259 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381680 Debug: 1905 86266 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381700 Debug: 1906 86273 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381780 Debug: 1907 86281 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381800 Debug: 1908 86287 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381880 Debug: 1909 86293 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381900 Debug: 1910 86299 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381980 Debug: 1911 86305 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a00 Debug: 1912 86313 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381a80 Debug: 1913 86319 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b00 Debug: 1914 86326 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381b80 Debug: 1915 86332 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c00 Debug: 1916 86339 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381c80 Debug: 1917 86345 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d00 Debug: 1918 86352 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x40381d80 Debug: 1919 86358 target.c:2185 target_free_working_area_restore(): freed 7648 bytes of working area at address 0x40380000 Debug: 1920 86364 target.c:1964 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes) Debug: 1921 86370 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000 Debug: 1923 86377 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84080 Debug: 1924 86385 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84100 Debug: 1925 86394 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84180 Debug: 1926 86401 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200 Debug: 1927 86407 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84280 Debug: 1928 86414 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84300 Debug: 1929 86420 riscv-013.c:3334 write_memory_bus_v1(): transferring burst starting at address 0x3fc84380 Debug: 1930 86425 target.c:2185 target_free_working_area_restore(): freed 932 bytes of working area at address 0x3fc84000 Debug: 1931 86431 target.c:1964 print_wa_layout(): 0x3fc84000-0x3fca3fff (131072 bytes) Error: 1932 86437 esp_flash.c:340 esp_flash_get_size(): Failed to run flasher stub (-4)! Error: 1933 86441 esp_flash.c:981 esp_flash_probe(): Failed to probe flash, size 0 KB Debug: 1934 86446 command.c:629 run_command(): Command 'flash probe' failed with error code -4 User : 1935 86451 command.c:694 command_run_line(): Debug: 1936 86453 riscv.c:483 riscv_deinit_target(): riscv_deinit_target() Debug: 1937 86456 riscv-013.c:1543 deinit_target(): riscv_deinit_target() Debug: 1938 86464 target.c:2218 target_free_all_working_areas_restore(): freeing all working are Debug: 1939 86471 target.c:1964 print_wa_layout(): 0x40380000-0x40383fff (16384 bytes)

before hot-plugging the USB Info : only one transport option; autoselect 'jtag' Info : esp_usb_jtag: VID set to 0x303a and PID to 0x1001 Info : esp_usb_jtag: capabilities descriptor set to 0x2000 Warn : Transport "jtag" was already selected Info : esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255 Info : clock speed 40000 kHz Info : JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0) Error: Abstract command ended in error 'busy' (abstractcs=0x10001102) Error: Timed out after 5s waiting for busy to go low (abstractcs=0x10001102). Increase the timeout with riscv set_command_timeout_sec. Error: libusb_bulk_write error: LIBUSB_ERROR_PIPE Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: esp_usb_jtag: device not found! Error: esp_usb_jtag: failed to revive USB device! Error: missing data from bitq interface Error: dmi_scan failed jtag scan Error: Failed read (NOP) at 0x16; value=0xffffffff, status=2 Error: libusb_bulk_write error: LIBUSB_ERROR_TIMEOUT Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: esp_usb_jtag: device not found! Error: esp_usb_jtag: failed to revive USB device! Error: missing data from bitq interface Error: dmi_scan failed jtag scan Error: failed write at 0x16, status=2 Error: libusb_bulk_write error: LIBUSB_ERROR_TIMEOUT Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: libusb_open() failed with LIBUSB_ERROR_ACCESS Error: esp_usb_jtag: device not found! Error: esp_usb_jtag: failed to revive USB device! Error: missing data from bitq interface Error: dmi_scan failed jtag scan Error: failed write at 0x17, status=2 Error: Fatal: Failed to read MISA from hart 0. Warn : target esp32c3 examination failed Info : starting gdb server for esp32c3 on 3333 Info : Listening on port 3333 for gdb connections Error: Target not examined yet

espressif / openocd-esp32

Unable to program blank ESP32-C3 chips (OCD-552) #228

Development Kit

Module or chip used

Debug Adapter

OpenOCD version

Operating System

Using an IDE ?

OpenOCD command line

JTAG Clock Speed

ESP-IDF version

Problem Description

Debug Logs

Expected behavior

Screenshots

=== Run "summary" command === EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)

Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default

'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map

Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default