ESP32-S3 in QEMU: PSRAM cannot work for esp32s3 device (QEMU-211)

[dongsheng28849455]

Checklist

• [x] Checked the issue tracker for similar issues to ensure this is not a duplicate.
• [ ] Described the feature in detail and justified the reason for the request.
• [ ] Provided specific use cases and examples.

Feature description

Is it possible to support PSRAM for S3 also?

Use cases

In nuttx nsh, we expect the umem can be 32M size. NuttShell (NSH) NuttX-12.6.0-RC1 nsh> free total used free maxused maxfree nused nfree Kmem: 359196 16612 342584 17000 342584 43 1 Umem: 33161212 10596 33150616 10984 33150616 9 1

Alternatives

No response

Additional context

When I try to enable the PSRAM, I met several issues: 1, Similar with #57, neither SPIRAM_SPEED_80M nor SPIRAM_SPEED_40M can work 2, The ESP32S3MMUEntry e value will be overwritten by e.reserved 4, dcache was created as rom device, so dbus address cannot be written 3, SSS_PSRAM does not attach to SPI1 for S3 machine 4, RAM size larger than 4 MB not supported, seems S3 can support 32M as maximum.

[igrr]

Yes, as you found, PSRAM support is not implemented for S3 yet.

We'll update this issue when that gets done.

[dongsheng28849455]

Yes, as you found, PSRAM support is not implemented for S3 yet.

We'll update this issue when that gets done.

Can I ask will you implement it recently?

[dongsheng28849455]

I try to fix it by #104, please help review it, thanks.

[o-marshmallow]

Hello @dongsheng28849455 ,

Sorry for not giving more updates about this. A few days ago, we opened an internal MR to add support for the PSRAM on the S3. It is currently under review.

[igrr]

PSRAM support for ESP32-S3 has been merged in https://github.com/espressif/qemu/commit/39534c3193c88417b1cc9836169f3433dfff42a5 and https://github.com/espressif/qemu/commit/89fe574c628124d0c2329ba8f05f892e685100df, will appear in the next release.

[dongsheng28849455]

Thanks for your works, when i test it, seems the get_eid_by_size does not handle the case of size_mbytes equal to 16M or 32M?

[igrr]

@dongsheng28849455 That's right. There are no commercially available 16MB or 32MB QSPI PSRAM chips yet, so neither IDF nor QEMU have defined an ID for them.

We have a work-in-progress MR for IDF and for QEMU which defines a couple of fake IDs, which don't correspond to any real PSRAM models. I'll ping you once these MRs are merged, then you will be able to copy the implementation into NuttX.

[dongsheng28849455]

hi, @igrr , Another question, for the psram spi data transfer, how can we set the dummy size except the time device init? I met some cases that demand the dummy being 0 or 1. can it be set dynamically? or any parameter we can set when loading the image?

[igrr]

In theory QEMU allows doing this from the CLI, e.g.

-global driver=ssi_psram,property=dummy,value=2

However, currently esp32s3_machine_init_psram function calls qdev_prop_set_uint32(psram, "dummy", 0), which overwrites any value set from the CLI.

Could you please describe your use case? Are you using a different PSRAM chip model which is incompatible with the setting chosen in esp32s3_machine_init_psram?

[dongsheng28849455]

sorry, here I mentioned is for esp32, just by adding and reading logs. seems the "dummy" must be set as 0 rather than 1 before it can work.

[igrr]

You are testing this on NuttX, right? Could this be some difference between IDF's PSRAM driver and NuttX driver? IDF's PSRAM driver uses dummy=1 on ESP32 and dummy=0 on ESP32-S3.

cc @tmedicci

[dongsheng28849455]

Yes, I'm testing nuttx, but a private one from apache. cc @donghengqaz, BTW, in current impl, seems no bytes in dummy phase insterted for esp32? (in cmd, addr, data sequence) refer to esp32_spi_transaction, thus the "dummy" in sss_psram must be 0.

but do have dummy for esp32s3 (in cmd, addr, dummy, data) (esp32_spi_transaction)

for driver, either nuttx or idf, aren't they supposed to follow the hw spec settings?

I can only find some spec for this, but not exactly one, in esp32-s3_technical_reference_manual_en.pdf, Figure 30-9. SPI Quad I/O Read Command Sequence Sent by GP-SPI2 to Flash, it defined a seqence for flash device, much like the psarm on S3