#enhancement: wavedrom bitfield adding `lanes` to csrconfig

[iDoka]

At this moment if I correct understand the lanes for wavedrom bitfield creation sliced for 16 bits per lane: https://github.com/esynr3z/corsair/blob/master/corsair/generators.py#L104

In generic case it is good solution but in some specific cases (almost all) would be nice manually specify number of lanes in csrconfig.

Just an example: my most adorable documentation - any datasheet from Atmel company. They use config 8 bits per lane and it is convenient way to have enough volume to print field name (even if it's not the shortest name):

Would be nice to have such flexibility in future release 🙏🏻

[arnfol]

I accidentally found out that now corsair always generates one-line registers, which is not an expected behavior. Maybe wavedrompy API changed

[malsheimer]

Hi @arnfol, I fixed the issue with wavedrompy API in the Class Wavedrom(). See my PR #43. Cheers.