With vivado (2021.2) as the simtool results in something like:
ERROR: [XSIM 43-4100] ".../corsair/tests/hdl/test_rmap/tb_ro.sv" Line 3. Module tb_ro has a timescale but at least one module in design doesn't have timescale.
for the verilog tests.
Need to either remove the timescale from those files, or add to other files for the test to pass.
Running:
With vivado (2021.2) as the simtool results in something like:
for the verilog tests.
Need to either remove the timescale from those files, or add to other files for the test to pass.