#4: verilog/VHDL: only generate access signal for specified access mode - Githubissues

esynr3z / corsair

Control and Status Register map generator for HDL projects

https://corsair.readthedocs.io

MIT License

97 stars 35 forks source link

#4: verilog/VHDL: only generate access signal for specified access mode #27

Closed v0lker closed 2 years ago

v0lker commented 2 years ago

see issue #4