A write-only register with Hardware 'access' option, uses a undeclared *_rdaccess signal

[nmmalipes]

When creating a write-only register with "oa" hardware access options, an undeclared signal is referenced in the code.

--------------------------------------------------------------------------------
-- CSR:
-- [0x108] - TEST_WO_OA - Test rolh
--------------------------------------------------------------------------------
csr_test_wo_oa_rdata(31 downto 1) <= (others => '0');

csr_test_wo_oa_wen <= wen when (waddr = "00000000000000000000000100001000") else '0'; -- 0x108

-----------------------
-- Bit field:
-- TEST_WO_OA(0) - WO_OA - test signal
-- access: wo, hardware: oa
-----------------------
csr_test_wo_oa_wo_oa_waccess <= wready and csr_test_wo_oa_wen;
csr_test_wo_oa_wo_oa_raccess <= rvalid and csr_test_wo_oa_ren;  -- THIS LINE CAUSES ERRORS 

csr_test_wo_oa_rdata(0) <= '0';

csr_test_wo_oa_wo_oa_out <= csr_test_wo_oa_wo_oa_ff;

process (clk) begin
if rising_edge(clk) then
if (rst = '1') then
    csr_test_wo_oa_wo_oa_ff <= '0'; -- 0x0
else
        if (csr_test_wo_oa_wen = '1') then
            if (wstrb(0) = '1') then
                csr_test_wo_oa_wo_oa_ff <= wdata(0);
            end if;
        else
            csr_test_wo_oa_wo_oa_ff <= csr_test_wo_oa_wo_oa_ff;
        end if;
end if;
end if;
end process;

The same happens with a read-only register with 'ia' access, where a _wraccess is undeclared.

[arnfol]

Are you using corsair installed from pip? Try to build it yourself from the master, this was solved in #4