Queue read not working when FIFO is ready in advance

[arnfol]

Queue q hardware interface with ro access misses read when data is already available. Tested on vhdl target.

The waves:

Here, zeros are read instead of FFFEFF+ or 000164+. That happens because of:

rvalid_drv <=
    csr_prediction_prediction_rvalid_ff when (csr_prediction_ren = '1') else
    rvalid_ff;

[arnfol]

After observing the q interface more closely I think it is a strange abomination of AXI-Stream and FIFO interfaces.

I would expect FIFO interface to never wait for !empty/rvalid when reading, but rather signal an underflow. Like in this picture: The case of underflow could, and probably should be solved by adding an additional interrupt register to the regmap manually and connecting it to external logic.

On the other hand, AXI-Stream interface would rise and hold ready/ren and wait for data to appear (the current interface only ticks ren).

I think it would be beneficial to support both FIFO and AXI-Stream interfaces.

[arnfol]

Dublicates #7