Fixed an error that occurred in the HDL (Verilog/VHDL) templates when bit fields are defined such that it results in a 1 bit wide 'reserved' field at position MSB.

[malsheimer]

Fixed an error that occurred in the HDL (Verilog/VHDL) templates when bit fields are defined such that it results in a 1 bit wide 'reserved' field at position MSB.

Example:

• regs.yaml

  
  regmap:

• name: DATA description: Data register address: 4 bitfields:

  • name: PERR2 description: Parity error flag. Read to clear. reset: 0 width: 1 lsb: 30 access: rolh hardware: i enums: []

• regs.v

  // CSR:
  // [0x4] - DATA - Data register
  //------------------------------------------------------------------------------
  wire [31:0] csr_data_rdata;
  assign csr_data_rdata[29:0] = 30'h0;

  FIXED:

  //------------------------------------------------------------------------------
  // CSR:
  // [0x4] - DATA - Data register
  //------------------------------------------------------------------------------
  wire [31:0] csr_data_rdata;
  assign csr_data_rdata[29:0] = 30'h0;
  assign csr_data_rdata[31] = 1'b0;

• regs.vhd

--------------------------------------------------------------------------------
-- CSR:
-- [0x4] - DATA - Data register
--------------------------------------------------------------------------------
csr_data_rdata(29 downto 0) <= (others => '0');

FIXED:

--------------------------------------------------------------------------------
-- CSR:
-- [0x4] - DATA - Data register
--------------------------------------------------------------------------------
csr_data_rdata(29 downto 0) <= (others => '0');
csr_data_rdata(31) <= '0';

[ttobsen]

We are also facing this problem. Would be nice if this could be approved asap. :smiling_face_with_tear:

[esynr3z]

Thank you for this fix a lot!