esynr3z / corsair

Control and Status Register map generator for HDL projects
https://corsair.readthedocs.io
MIT License
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c-headers: struct and bit field layout are implementation defined... #52

Open v0lker opened 1 year ago

v0lker commented 1 year ago

as we all know from the standard (or references), the compiler is free to arrange the data as it likes[1]. it seems advisable to put a pragma pack around the structs and annotate the struct members with attribute packed ?

it doesn't suffice to just access the members properly (like in [2]) - we also need to guarantee that the bits are in the same location as they are for the FPGA side.

the only way to fix this that i know of would be to generate packing/un-packing code that uses e.g. logical operations, but that's quite tedious. it might be enough to be able to detect this issue, though? (not that that's much easier...)

thoughts?

[1] https://www.open-std.org/JTC1/SC22/WG14/www/docs/n1256.pdf §6.7.2.1.10: "An implementation may allocate any addressable storage unit large enough to hold a bit- field. [...] The order of allocation of bit-fields within a unit (high-order to low-order or low-order to high-order) is implementation-defined. The alignment of the addressable storage unit is unspecified."

for GCC it depends on the ABI: https://gcc.gnu.org/onlinedocs/gcc/Structures-unions-enumerations-and-bit-fields-implementation.html

[2] https://wiki.sei.cmu.edu/confluence/display/c/EXP11-C.+Do+not+make+assumptions+regarding+the+layout+of+structures+with+bit-fields