Verilog build failed when using multistring description

[iDoka]

csrconfig:

[globcfg]
base_address  = 0
data_width    = 16
address_width = 8
register_reset = async_neg
address_increment = none
address_alignment = none
force_name_case = none
regmap_path = exam.yaml

[v_module]
generator = Verilog
path = exam.v
read_filler = 0
interface = lb

exam.yaml:

regmap:
-   name: EXAM
    description: Examinate
    address: 1
    bitfields:
    -   name: exam
        description: |
            Examinate multistring values in yaml:
            0 - disable
            1 - enable
        reset: 0
        width: 1
        lsb: 0
        access: wo
        hardware: o
        enums: []
    -   name: none
        description: none description
        reset: 0
        width: 1
        lsb: 1
        access: rw
        hardware: io
        enums: []

exam.v:

...
//---------------------
// Bit field:
// EXAM[0] - exam - Examinate multistring values in yaml:
0 - disable
1 - enable

// access: wo, hardware: o
//---------------------
...

Syntax check:

verible-verilog-syntax playground/exam.v

playground/exam.v:51:1: syntax error at token "0"
playground/exam.v:52:1: syntax error at token "1"