Hi! I really like the project and would see a ton of use for it in our FPGA/ASIC projects. However, one blocker I see is the lack of parameters on the HDL modules generated. I often have multiple instances of a module that I would like to share the same register bank. For this I often have modules that look like this in Verilog:
I would this type of Register to be supported by corsair. This is a larger feature request that I would be happy to collaborate to. I would like your feedback on how best to include this. I was thinking of adding a class like UnpackedRegisters that would take in input a Register object and a name for its parameter.
Is this a feature that you would like to be supported and is my proposed approach in line to how you would approach the issue?
Hi! I really like the project and would see a ton of use for it in our FPGA/ASIC projects. However, one blocker I see is the lack of parameters on the HDL modules generated. I often have multiple instances of a module that I would like to share the same register bank. For this I often have modules that look like this in Verilog:
I would this type of Register to be supported by corsair. This is a larger feature request that I would be happy to collaborate to. I would like your feedback on how best to include this. I was thinking of adding a class like
UnpackedRegisters
that would take in input aRegister
object and a name for its parameter.Is this a feature that you would like to be supported and is my proposed approach in line to how you would approach the issue?