Support for parametrized unpacked arrays

[g-lesssard]

Hi! I really like the project and would see a ton of use for it in our FPGA/ASIC projects. However, one blocker I see is the lack of parameters on the HDL modules generated. I often have multiple instances of a module that I would like to share the same register bank. For this I often have modules that look like this in Verilog:

module registers #(
   parameter DATA_W = 32,
   parameter INSTANCE_COUNT = 8
) (
...
output [INSTANCE_COUNT-1:0] control_reg [DATA_W-1:],
...
);

I would this type of Register to be supported by corsair. This is a larger feature request that I would be happy to collaborate to. I would like your feedback on how best to include this. I was thinking of adding a class like UnpackedRegisters that would take in input a Register object and a name for its parameter.

Is this a feature that you would like to be supported and is my proposed approach in line to how you would approach the issue?

[esynr3z]

Hi! Indeed, this is frequently requested feature. I thought about it myself when creating 1.0, but in order to simplify things it was postponed. Now I'm working on 2.0 and this a good time to make some architectural tweaks to facilitate this kind of feature integration in the future.