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etf-unibl / fpga-pwg

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Dopunjena verzija testbenča za brojač i izlaznu logiku #6

Closed RadonicA closed 8 months ago

RadonicA commented 9 months ago

Implementacija testbench-a koji će provjeravati ispravnost funkcionalnosti izlazne logike i brojača zajedno. Rezultat ovog zadatka je VHD fajl kojim se potvrdjuje ispravnost, te simulacija kojom se potvrdjuje zeljeni rad.

RadonicA commented 8 months ago

Rezultat simulacije:

Image

RadonicA commented 8 months ago

Log simulacije:

../../src/ieee/v93/numeric_std-body.vhdl:1613:7:@0ms:(assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE tb_top.vhd:121:30:@200ns:(report note): OK, generated H at specified time stamp tb_top.vhd:127:28:@540ns:(report note): OK, generated L at specified time stamp tb_top.vhd:121:30:@940ns:(report note): OK, generated H at specified time stamp tb_top.vhd:121:30:@1240ns:(report note): OK, generated H at specified time stamp tb_top.vhd:127:28:@1600ns:(report note): OK, generated L at specified time stamp