This PR updates the dc example to correctly start distributed clock SYNC0 cycles at a point in the future so that the MainDevice can sync to the DC System Time and maintain a constant offset.
The example uses an offset of 50% on a 5ms cycle time, i.e. the process data is sent 2.5ms after the SYNC0 pulse. This has been checked against a LAN9252 dev board, looking at the SYNC0 and IRQ pins on an oscilloscope.
MainDevice jitter is also compensated for by adding a variable delay to the next process data cycle. This produces very consistent MainDevice cycle ticks - we're down into microseconds of jitter on my test system.
This PR updates the
dcexample to correctly start distributed clock SYNC0 cycles at a point in the future so that the MainDevice can sync to the DC System Time and maintain a constant offset.The example uses an offset of 50% on a 5ms cycle time, i.e. the process data is sent 2.5ms after the SYNC0 pulse. This has been checked against a LAN9252 dev board, looking at the SYNC0 and IRQ pins on an oscilloscope.
MainDevice jitter is also compensated for by adding a variable delay to the next process data cycle. This produces very consistent MainDevice cycle ticks - we're down into microseconds of jitter on my test system.