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etherkit / Si5351Arduino

Library for the Si5351 clock generator IC in the Arduino environment
GNU General Public License v3.0
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It would be nice to easily have CLK0 and CLK1 in phase.... #75

Closed frohro closed 3 years ago

frohro commented 3 years ago

Hi, Ideally, I would like CLK0 to go at twice the frequency of CLK1, but have them in phase. That way I can drive the low and high order control bytes of a 4x1 analog MUX for doing SDR to end up with I and Q. (It counts 00, 01, 10, 11,..., where the low order bit is half the frequency of the high bit.) I think the restrictions that occur with a 90 degree phase delay between CLK0 and CLK1 do not occur with this setup because the phase delay is zero. It would be nice to let the library deal with the intricacies though. ;-) This scheme is used by Guido in the UCX-SSB, but he isn't using your handy library. I would like it to be easy for those who prefer the library route. Thanks & 73, Rob KL7NA

NT7S commented 3 years ago

Hello,

Have you tried setting each CLK output to the same phase with the set_phase method after setting the frequency? If I understand what you are trying to do correctly, that should be what you are looking for. From my experiments in trying to generate PSK with the Si5351A, I do know that you can set both outputs to the same phase as long as you don't change the frequency again. Once you do, you have to reset the phase (and there's a discontinuity in the waveform).

Better yet, you might want to set CLK0 as desired, and then set CLK1 to get its clock from CLK0 and then use the set_ms method and use the R_DIV divider of CLK1 to divide by two. I should think that would guarantee phase fidelity, but I haven't tried it to verify that. I'm going to close the issue on the assumption that one of the two methods will work for you, but if not, feel free to comment some more.

la3pna commented 3 years ago

Going to be a PITA and open this issue again for a comment:

Option 2 as outlined by Jason works and are tested here.

FWIW, you can't have anything be in phase and on different frequencies at the same time. What you want is to have the leading edges synchronized or clocked.

BR. Thomas.

tor. 6. aug. 2020 kl. 23:51 skrev Jason Milldrum notifications@github.com:

Hello,

Have you tried setting each CLK output to the same phase with the set_phase method after setting the frequency? If I understand what you are trying to do correctly, that should be what you are looking for. From my experiments in trying to generate PSK with the Si5351A, I do know that you can set both outputs to the same phase as long as you don't change the frequency again. Once you do, you have to reset the phase (and there's a discontinuity in the waveform).

Better yet, you might want to set CLK0 as desired, and then set CLK1 to get its clock from CLK0 and then use the set_ms method and use the R_DIV divider of CLK1 to divide by two. I should think that would guarantee phase fidelity, but I haven't tried it to verify that. I'm going to close the issue on the assumption that one of the two methods will work for you, but if not, feel free to comment some more.

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frohro commented 3 years ago

Hi Thomas,

Any chance you could provide me an example?

Thanks,

Rob

On 8/6/20 10:34 PM, Thomas S. Knutsen wrote:

CAUTION: This email originated from outside the Walla Walla University email system.

Going to be a PITA and open this issue again for a comment:

Option 2 as outlined by Jason works and are tested here.

FWIW, you can't have anything be in phase and on different frequencies at the same time. What you want is to have the leading edges synchronized or clocked.

BR. Thomas.

tor. 6. aug. 2020 kl. 23:51 skrev Jason Milldrum notifications@github.com:

Hello,

Have you tried setting each CLK output to the same phase with the set_phase method after setting the frequency? If I understand what you are trying to do correctly, that should be what you are looking for. From my experiments in trying to generate PSK with the Si5351A, I do know that you can set both outputs to the same phase as long as you don't change the frequency again. Once you do, you have to reset the phase (and there's a discontinuity in the waveform).

Better yet, you might want to set CLK0 as desired, and then set CLK1 to get its clock from CLK0 and then use the set_ms method and use the R_DIV divider of CLK1 to divide by two. I should think that would guarantee phase fidelity, but I haven't tried it to verify that. I'm going to close the issue on the assumption that one of the two methods will work for you, but if not, feel free to comment some more.

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub

https://github.com/etherkit/Si5351Arduino/issues/75#issuecomment-670209830, or unsubscribe

https://github.com/notifications/unsubscribe-auth/ABBYNPEPBT5JMYSXRBTCPH3R7MQXXANCNFSM4PU6HQXQ .

-- With Best regards, Thomas S. Knutsen.

Please avoid sending me Word or PowerPoint attachments.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://nam05.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fetherkit%2FSi5351Arduino%2Fissues%2F75%23issuecomment-670334627&data=02%7C01%7Crob.frohne%40wallawalla.edu%7C5e73a06255ef438f693108d83a9395be%7Cd958f048e43142779c8debfb75e7aa64%7C0%7C0%7C637323752850397525&sdata=wdvJXUIl0cLKLvSj3m0Yu2uc3J2yDNjgHFcRebkCzEY%3D&reserved=0, or unsubscribe https://nam05.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fnotifications%2Funsubscribe-auth%2FAAHS2BKQ53BONHBUST4M5ZTR7OG7DANCNFSM4PU6HQXQ&data=02%7C01%7Crob.frohne%40wallawalla.edu%7C5e73a06255ef438f693108d83a9395be%7Cd958f048e43142779c8debfb75e7aa64%7C0%7C0%7C637323752850402514&sdata=6u262YPoNfvgzbn%2Bw8lmIiws0QEFY%2FKWiVX6vA5fSl8%3D&reserved=0.

-- Rob Frohne, Ph.D. P.E. E. F. Cross School of Engineering Walla Walla University 100 SW 4th Street College Place, WA 99362 (509) 527-2075

frohro commented 3 years ago

I really think the idea of setting the output divider as divide by two for the slower clock is what I need to do, but I can't figure out how to get the struct Si5351RegSet ms_reg needed for the set_ms method. An example would be best, but if I could even figure that out, it might solve my entire problem. Thanks! Rob