Delay between CLK0 and CLK1

[mrguen]

Describe the bug I am not quite sure this is a bug related to the library or not.

I was setting both clocks 0 and 1 @ 80 MHz with the same phase (0) and saw that CLK0 is in advance of 45 degrees.

Since my code does configure the Si5351 I was wondering if it was done the right way.

So I tried the example sketch "si5351_phase.ino". At first it seemed the two clocks are delayed by 90°. But in fact if you set both clocks at phase = 0 you will see that there is a remaining delay. CLK0 is in advance of about 10°. It gets worse @80 MHz.

To Reproduce

• Use the sketch "si5351_phase.ino"

• Change the parameters unsigned long long freq = 8000000000ULL; unsigned long long pll_freq = 80000000000ULL;

• Set phases to "0" si5351.set_phase(SI5351_CLK0, 0); si5351.set_phase(SI5351_CLK1, 0);

• Upload the sketch

You can see that CLK0 is clearly in advance of CLK1

[semiversus]

I guess a PLL reset would be required (like si5351.pll_reset(SI5351_PLL_RESET_A))