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eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
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Kria KV260 support #124

Closed Chamusuke closed 1 year ago

Chamusuke commented 1 year ago

Hellow, I find your posts very helpful. I have a KV260. I want to run Debian on RISC-V on Zynq PL, not on an ARM CPU on a Zynq PS. Is there any advice and convenient way?

mwrnd commented 1 year ago

I too am working on a similar project. I want to run a RISC-V system entirely in Programmable Logic and memory. I use PCIe-to-AXI (XDMA) and the Zynq equivalent would be AXI PS-PL Interfaces.

A RISC-V system requires five "external" interfaces; RAM, storage, UART, Ethernet, and JTAG. My idea would be to use the Zynq to translate the various protocols for the RISC-V and host it.

RISCV_Zynq

RAM and storage can be combined by using tmpfs as a boot drive similar to Live Linux systems. The KV260 shares memory between the PS and PL so the 4GB would need to be divided up among the Zynq, RISC-V, and RISC-V storage. Note debian-riscv64.sd.img.gz extracts into a 1.6GB file.

The UART and Ethernet would then need to be tunneled. The Xilinx Virtual Cable should allow JTAG over AXI.

I am stuck on 1) boot a combined RAM+storage Linux image (Live-in-RAM RISC-V System) 2) xsdb to OpenOCD xlnx_pcie_xvc communication 3) Ethernet Tunnel over AXI

There is a discussion on PCIe Cards but it does not appear @Rucadi completed the project. ssith-aws-fpga has some drivers worth exploring.

Any suggestions will be appreciated.

Rucadi commented 1 year ago

While I have not completed the project, due to me no longer working at the company that requiered it, the project on my repo is working for the alveo, and it integrates the opensbi+u-boot in the bootrom.

1- Just use u-boot, once you have u-boot, load a fitimage with linux. If you can't bring up a shell in the initramfs, you could try with a disk in memory: https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/pmem/pmem-region.txt

2- Can't help you

3- If you want to achieve the ethernet over pcie, it can be done more or less "easily" modifying this driver to talk through PCIe (https://github.com/eugene-tarassov/vivado-risc-v/blob/master/patches/fpga-axi-eth.c) (I recommend fixing the addresses instead of dynamically allocating them).

Then you just have to use that module as-is on the rocket part, and your modified driver on the host.

Another solution, but less efficient, could be to create a TUN/TAP driver over uncached memory seen by both, pci and the rocket.

Creating a simple ethernet tunnel over pci/axi is simple (The hard part is understanding what to do), making it efficient by yourself probably is harder.