eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
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Custom Instructions #128

Closed reitowo closed 5 months ago

reitowo commented 1 year ago

Hi, sorry to bother you!

I'm very new to RISCV, and I want to add my custom instructions to this project, and I found RocketChip has something useful: https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/scie/SCIE.scala . Is it possible to modify this file in the middle of make, or should I specify a fork of the whole rocket-chip design with my own modification?

I also learned something named RoCC, is that the same as Gemmini accelerator? How do I modify the Makefile to add a custom RoCC to the design?

I don't know how to easily integrate to this project, and make everything work, do you have related suggestions?

Thank you!

eugene-tarassov commented 1 year ago

I think the best way is to create a new repo and include this repo as submodule. In your repo, you can add your own Scala files to extend RocketChip functionality, setup SBT project, add Makefile, etc. You should not need to modify anything in the submodule, you can just refer to it from SBT and Makefile.

I also learned something named RoCC, is that the same as Gemmini accelerator?

RoCC is RocketChip interface for adding processor extensions, Gemmini is an example of such extension that uses RoCC.

reitowo commented 1 year ago

Thanks, I'll try figure it out

reitowo commented 1 year ago

Does this sound right?

eugene-tarassov commented 1 year ago

Yes.

One more thing: Scala is built by SBT (Scala Build Tool), so you will need SBT config files: build.sbt, project/build.properties and project/plugins.sbt.

reitowo commented 1 year ago

Thank you very much!