Hello, my application scenario requires a DDR3 controller with axi interface, so I generated my DDR3 source code based on the stlv7325 development board. However, even if DDR3 initialization is successful during use, there may be issues with DDR reading and writing data failure.
In order to verify the data read and write issues of the axi interface, I connected the axi interface of the litedram core to the official mig example of xilinx. After successful DDR initialization, I found that the axi interface of the litedram core can read data normally, as follows:
However, the write data failed, and the write preparation signal remained low, as follows:
From the picture, it can be seen that the writing error signal write_err has also been raised. May I ask if this is due to the different functions of the Litedram core and Mig design, which caused the testing to fail in the official Mig testing example of Xilinx, or is it because I overlooked which part was not set properly?
Hello, my application scenario requires a DDR3 controller with axi interface, so I generated my DDR3 source code based on the stlv7325 development board. However, even if DDR3 initialization is successful during use, there may be issues with DDR reading and writing data failure. In order to verify the data read and write issues of the axi interface, I connected the axi interface of the litedram core to the official mig example of xilinx. After successful DDR initialization, I found that the axi interface of the litedram core can read data normally, as follows:
However, the write data failed, and the write preparation signal remained low, as follows:
From the picture, it can be seen that the writing error signal write_err has also been raised. May I ask if this is due to the different functions of the Litedram core and Mig design, which caused the testing to fail in the official Mig testing example of Xilinx, or is it because I overlooked which part was not set properly?