Open AminSavari opened 5 months ago
Additional Verilog sources, like RoccBlackBox.v, are supposed to be added to Vivado project file, not to system-vc707.v, which is generated from Chisel. The project file is created by vivado.tcl script. You can modify the script to include more Verilog files.
Hello,
I have my top module in verilog. I included it in RoccBlackBox.v which is in
rocket_chip/src/main/resources/vsrc/
. I also changed the configuration file Configs.scala inrocket_chip/src/main/scala/subsystem/
. I changed the WithRoccExample class to this:then in vivado-riscv/src/main/scala/rocket.scala, I added this:
When I try
$make CONFIG=rocket64bb BOARD=vc707 bitstream
I get:Then When I try to add the content of RoccBlackBox.v to system-vc707.v I get these warning:
which will result to a failed synthesis. Could you please tell me why RoccBlackBox.v is not automatically included in system-vc707.v and what I am doing wrong?