eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
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make CONFIG=rocket64b2 BOARD=nexys-a7-100t bitstream fail #222

Open sasakiakaya opened 5 months ago

sasakiakaya commented 5 months ago

vivado version:2022.2

echo "set_param general.maxThreads 1" >>workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl echo "open_project workspace/rocket64b2/vivado-nexys-a7-100t-riscv/nexys-a7-100t-riscv.xpr" >workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl echo "update_compile_order -fileset sources_1" >>workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl echo "reset_run synth_1" >>workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl echo "launch_runs -jobs 1 synth_1" >>workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl echo "wait_on_run synth_1" >>workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl env XILINX_LOCAL_USER_DATA=no vivado -mode batch -nojournal -nolog -notrace -quiet -source workspace/rocket64b2/vivado-nexys-a7-100t-riscv/make-synthesis.tcl INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to 'no'. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/sasakiakaya/github/FPGA/vivado-risc-v/workspace/rocket64b2/vivado-nexys-a7-100t-riscv/nexys-a7-100t-riscv.gen/sources_1'. Scanning sources... Finished scanning sources CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the fileset sources_1. Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow. CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the fileset sources_1. Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow. WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. ERROR: [Common 17-53] User Exception: Top module not set for synthesis run Ensure that a valid value is provided for 'top'. The current value for 'top' can be changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command