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eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
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Problems when recompiling the bootrom with a new maskrom_mem address range and a new dtb address #233

Open Caiyujie007 opened 3 weeks ago

Caiyujie007 commented 3 weeks ago

In the original design of Rocketchip, the dtb is fixed in the ROM code. I want to change the dtb after the bitstream is generated, so I add a SRAM on the MEM AXI4 BUS with address range (0xA0000000, 0xA0000000+0x00010000). I plan to upload the newly compiled bootrom.elf (with modified dtb) into the SRAM and then jump the PC to 0xA0000040 using JTAG. But I encountered a problem when recompiling bootrom.elf. I firstly change the maskrom_mem address definition in "bootrom.lds", as : MEMORY { error_mem (rw) : ORIGIN = 0x00003000, LENGTH = 0x00001000 maskrom_mem (rx) : ORIGIN = 0xA0000000, LENGTH = 0x00010000 memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00002000 } Then recompile the bootrom.elf, download and execute bootrom.elf using JTAG. The debian OS can boot up, but I find that the device tree leaves unchanged. Then, I found there is a macro definition of "BOOTROM_DTB_ADDR" in "common.h", so I changed the value of "BOOTROM_DTB_ADDR" into :

define BOOTROM_DTB_ADDR 0xA0000080

Then, I recompile the bootrom.elf, download and execute bootrom.elf using JTAG again, but found that the OpenSBI cannot be launched. How can I launch the debian OS with the newly compiled dtb at address 0xA0000080? Thanks.

Caiyujie007 commented 2 weeks ago

I am currently modifying the generated Verilog code (system-XXX.v) to turn TLROM into a RAM that can be written externally. Then I used the AXI2SRAM IP to re-download the contents of TLROM via JTAG. Currently, I can modify the dtb after generating the bitstream, but there should be a more elegant way if the address of dtb (i.e., the value of register a1) can be modified.