eurus13
commented
4 years ago Hope this message finds you well. Sorry for the slow reply, I started to type out of response and realized I needed to add that info to the Github, so I wanted to only write it once.
I agree, it seems spoofing won't work for a lot of reasons.
I found theMicron (MT16KTF2G64HZ) Data sheet. It's my understanding Crucial is their retail division.
I added what I've found to the Github. Looks like we had some of the same solutions in the MRC address decode file, but diverged on some others. I am not fluent in C so I will want to double check before it's implemented.
Here are my suggestions as well as the notes I added for myself
if (!get_lpddr_mode(MAD_CHNL) { return (dimm_rank_size_as_cl == HSW_MC_16GB_AS_CL) ? 11 : 10; <----------------- 11 else 10
//the condition would be read aa if not lpddr and if rank_size_as_cl = 16gb then col = 11, otherwise col = 10
// remove this two lines below
- return 10; // Supported DDR3 DRAM organizations all have 10 column bits
- return (dimm_rank_size_as_cl == HSW_MC_16GB_AS_CL) ? 11 : 10;
// after removed leave the following bracket
}// LPDDR3 is only soldered aka memory down and which will never be the case for T440p <--- notes
// If we got past the above line, we are LPDDR
width = get_dimm_a_width(MAD_CHNL, MAD_DIMM);
-
dimm_rank_size_as_cl = get_dimm_a_rank_size_as_cl(MAD_DIMM); if (width == 16) { return (dimm_rank_size_as_cl == HSW_MC_1GB_AS_CL) ? 10 : 11; // LPDDR x16 2Gb device has 10 col bits, // the 4 and 8 Gb LPDDR x16s have 11 col bits.
Anyways let me know if you have any questions!
BayLee4
Hi, would be easier to answer here I guess :)
You were right about me using a DDR3L module, this module to be exact. (They removed it from their website, had to use the wayback machine, the reference is Crucial CT204864BF160B 16Go)
I dumped the SPD some times ago, here is the result :
Also, I think spoofing the SPD to simulate a LPDDR3 would unfortunately not work, unless I misunderstood something, looking at the AddrDecode/Encode code, it looks like the MRC is using some kind of hacks to works with the eventual use of an 11 column, this code for instance seems to assume that the LPDDR3 will not use more than 15 row : but any 16GB module will use 16 row.
I tried to modify the code in order to enable the use of an 11 column for DRR3/L (diff.txt attached to this post), but I made a mistake : you will notice that in the file MrcHswMcAddrDecode.c I do some modification in a else statement which only concern "single rank or no rank interleaving", which my module is not (it has rank interleaving). I did not understand fully the logic of encoding/decoding the memory address there, and I am not able to build the BIOS on my own (I do not own the necessary proprietary Visual eBIOS tool to do that): I was relying on the good will of a chinese manufacturer of which I bought an Haswell SBC running a AMI Bios similar to the one that leaked.
diff.txt