[PATCH] This patchs adds support for CACHELINE_ALIGNED values for PPC.

[GoogleCodeExporter]

This patchs adds support for CACHELINE_ALIGNED values for PPC. I decided to 
hardcode the cacheline size to 128, since it is used on latest PowerPC chips 
(POWER6 and POWER7), however some more logic maybe need for different processor 
(for instance, some PPC A2 has 64 bytes cacheline size).

--- a/src/base/basictypes.h
+++ b/src/base/basictypes.h
@@ -331,8 +331,12 @@ class AssignAttributeStartEnd {

 #endif  // HAVE___ATTRIBUTE__ and __ELF__ or __MACH__

-#if defined(HAVE___ATTRIBUTE__) && (defined(__i386__) || defined(__x86_64__))
-# define CACHELINE_ALIGNED __attribute__((aligned(64)))
+#if defined(HAVE___ATTRIBUTE__)
+# if (defined(__i386__) || defined(__x86_64__))
+#   define CACHELINE_ALIGNED __attribute__((aligned(64)))
+# elif (defined(__PPC__) || defined(__PPC64__))
+#   define CACHELINE_ALIGNED __attribute__((aligned(16)))
+# endif
 #else
 # define CACHELINE_ALIGNED
 #endif  // defined(HAVE___ATTRIBUTE__) && (__i386__ || __x86_64__)

Original issue reported on code.google.com by zatr...@gmail.com on 25 Jul 2012 at 4:33

[GoogleCodeExporter]

Patch applied and committed to the main trunk.

------------------------------------------------------------------------
r156 | chappedm@gmail.com | 2012-09-17 21:18:15 -0400 (Mon, 17 Sep 2012) | 1 
line

issue-456: Adds support for CACHELINE_ALIGNED values for PPC
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Original comment by chapp...@gmail.com on 18 Sep 2012 at 1:23

• Changed state: Fixed