[PATCH] This patch adds support for CACHELINE_ALIGNED value for arm devices

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 This patch adds support for CACHELINE_ALIGNED value for arm
 devices. I hardcode the cacheline size to 32 because this
 value is supported by several arm devices, however a better
 logic needs to be implemented to handle more arm devices.

---
 src/base/basictypes.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/base/basictypes.h b/src/base/basictypes.h
index baaa806..db12a26 100644
--- a/src/base/basictypes.h
+++ b/src/base/basictypes.h
@@ -334,6 +334,8 @@ class AssignAttributeStartEnd {
 #if defined(HAVE___ATTRIBUTE__)
 # if (defined(__i386__) || defined(__x86_64__))
 #   define CACHELINE_ALIGNED __attribute__((aligned(64)))
+# elif defined(__arm__)
+#   define CACHELINE_ALIGNED __attribute__((aligned(32)))
 # elif (defined(__PPC__) || defined(__PPC64__))
 #   define CACHELINE_ALIGNED __attribute__((aligned(16)))
 # endif
-- 

Original issue reported on code.google.com by itrindad...@gmail.com on 13 Nov 2012 at 12:31

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Original comment by chapp...@gmail.com on 22 Dec 2012 at 5:46

• Changed state: Accepted

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r184 | chappedm@gmail.com | 2012-12-22 13:34:43 -0500 (Sat, 22 Dec 2012) | 7 
lines

issue-488: Performance improvement for initialization checks

These came in from the Google-internal version of tcmalloc. They saw some
decent speed improvements, both on microbenchmarks and big programs. The
idea is to improve the speed of the "Is everything initialized?" type of
code, that's at the start of all allocations and deallocations.

Original comment by chapp...@gmail.com on 22 Dec 2012 at 6:42

• Changed state: Fixed