evka85 GEM_AMC issues - Githubissues

evka85 / GEM_AMC

GEM uTCA AMC common firmware logic as well as board specific implementations for GLIB (Virtex 6) and CTP7 (Virtex 7)

0 stars 11 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Adding gbt_ic_controller Read Capability Disscussion

#41 rodwyer100 opened 5 years ago
0
Potential Bug When Writing GEM_AMC.SLOW_CONTROL.SCA.CTRL.TTC_HARD_RESET_EN Post 3.8.4??

#40 bdorney closed 5 years ago
3
New Bug in UHAL Address Tables?

#39 bdorney opened 5 years ago
11
[Version 3.8.3] Sbit monitor always reports wrong clusters

#38 lpetre-ulb opened 5 years ago
1
[bug] UHAL address tables generated incorrectly

#37 jsturdy closed 5 years ago
3
Drop `BxmAvO` and Add VFATX vs. VFATY Mismatch Flags in FW & Event Format

#36 bdorney opened 5 years ago
2
VFAT & AMC BX Mismatch no longer set to 0 automatically

#35 bdorney opened 5 years ago
0
removing bit files [v2_pma_clk]

#34 bdorney closed 5 years ago
0
removing bit files [v3_pre_promless]

#33 bdorney closed 5 years ago
0
removing bit files [v3]

#32 bdorney closed 5 years ago
0
New Feature: gemloader scripts now automatically determine bitfile size in bytes

#31 bdorney closed 5 years ago
1
removing bit files [master]

#30 bdorney closed 5 years ago
0
GE2/1 OH promless programming

#29 mexanick opened 5 years ago
6
[feature request] Package scripts into RPM for installation

#28 jsturdy opened 5 years ago
0
[Version 3.7.0] Trigger links are always reported in an healthy state

#27 lpetre-ulb closed 5 years ago
1
[Version 3.7.0] Address tables only contain 12OH's

#26 lpetre-ulb closed 5 years ago
1
Implement new FPGA <--> GBT tx/rx for GE2/1 and GE1/1 common protocol

#25 andrewpeck closed 5 years ago
0
[bug] generate_registers.py generates an invalid `uhal` address table for the BLASTER RAM

#24 jsturdy closed 5 years ago
4
Update test_phase_shifting.py

#23 jsturdy closed 5 years ago
0
Request: Change TTC_HARD_RESET_EN Default to 0x0 in v3.X.Y FW Releases

#22 bdorney opened 6 years ago
0
Bug Report: Divergence Between scripts on CTP7 and XHAL used in Central Repo

#21 bdorney opened 6 years ago
0
Bug Report: GEM_AMC Address Table Does Not have XInclude Lines

#20 bdorney closed 5 years ago
1
Bug Report: sca.py wipes FW of all FPGA's regardless of link Mask

#19 bdorney closed 5 years ago
4
Update to uhal generated address table

#18 jsturdy closed 6 years ago
0
Ability to determine which clock is currently driving the TTC decoder

#17 jsturdy opened 6 years ago
0
Naming conventions with releases

#16 jsturdy opened 7 years ago
0
Feature Request: Unify Address Table Format

#15 bdorney closed 5 years ago
0
Feature Request: VFAT Numbering Matches Current Convention

#14 bdorney closed 5 years ago
0
Scan module config

#13 jsturdy closed 7 years ago
0
Allow OH specific uhal address table to include some parts of the DAQ module

#12 jsturdy closed 7 years ago
1
clean_up

#11 mexanick opened 7 years ago
0
Fixed one more bug

#10 jsturdy closed 7 years ago
0
Use generate for VFAT ChanReg

#9 jsturdy closed 7 years ago
8
OH address table updates split

#8 jsturdy closed 7 years ago
1
Updated address table for new OH registers

#7 jsturdy closed 7 years ago
1
Update trigger link data format

#6 andrewpeck closed 8 years ago
3
Allow single vfat, show vfat IDs

#5 robertdkingjr closed 8 years ago
0
Color implemented, cleaner and easier to read output

#4 robertdkingjr closed 8 years ago
0
Latest code

#3 robertdkingjr closed 8 years ago
0
Prettier printout, masking implemented

#2 robertdkingjr closed 8 years ago
0
Reg Interface tool

#1 robertdkingjr closed 8 years ago
0