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commented
5 months ago Lint Status
The following issues have been found with 29556-RISCV_Support_COREV_XCVMEM_extension-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.
=== ERROR type #1: blocks of 8 spaces should be replaced with tabs (39 error(s)) ===
gcc/common/config/riscv/riscv-common.cc:1734:12: {"xcvmem",████████&gcc_options::x_riscv_xcv_subext, MASK_XCVMEM},
gcc/config/riscv/constraints.md:271:0:████████████████&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
gcc/config/riscv/constraints.md:272:0:████████████████&& GET_CODE (XEXP (XEXP (op, 0), 1)) == REG")))
gcc/config/riscv/constraints.md:279:0:████████████████&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
gcc/config/riscv/constraints.md:280:0:████████████████&& GET_CODE (XEXP (XEXP (op, 0), 1)) == REG)
gcc/config/riscv/constraints.md:288:0:████████████████████████████████████████████████ MEM_ADDR_SPACE (op))")
gcc/config/riscv/constraints.md:289:0:████████ (not (match_test "((GET_CODE (XEXP (op, 0)) == PLUS
gcc/config/riscv/constraints.md:290:0:████████████████&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
gcc/config/riscv/constraints.md:291:0:████████████████&& GET_CODE (XEXP (XEXP (op, 0), 1)) == REG)
gcc/config/riscv/constraints.md:292:0:████████████████|| GET_CODE (XEXP (op, 0)) == POST_MODIFY)
gcc/config/riscv/constraints.md:293:0:████████ && TARGET_XCVMEM")))))
gcc/config/riscv/corev.md:715:0:████████ (match_operand:ANYI 1 "mem_post_inc" "CV_mem_post"))]
gcc/config/riscv/corev.md:731:0:████████ (match_operand:ANYF 1 "mem_post_inc" "CV_mem_post"))]
gcc/config/riscv/corev.md:742:0:████████ (match_operand:ANYI 1 "register_operand" "r"))]
gcc/config/riscv/corev.md:750:0:████████ (match_operand:ANYF 1 "register_operand" "r"))]
gcc/config/riscv/corev.md:762:0:████████ (match_operand:ANYI 1 "mem_plus_reg" "CV_mem_plus"))]
gcc/config/riscv/corev.md:778:0:████████ (match_operand:ANYF 1 "mem_plus_reg" "CV_mem_plus"))]
gcc/config/riscv/corev.md:797:0:████████(match_operand:ANYF 1 "register_operand" " r"))]
gcc/config/riscv/corev.md:812:0:████████(match_operand:SI 1 "move_operand" " r,T,CV_mem_nopm,rJ,*r*J,*CV_mem_nopm,*f,*f,vp"))]
gcc/config/riscv/corev.md:816:0:████████ && reg_or_subregno (operands[1]) == VL_REGNUM)"
gcc/config/riscv/corev.md:825:0:████████(match_operand:HI 1 "move_operand"████████ " r,T,CV_mem_nopm,rJ,*r*J,*f,vp"))]
gcc/config/riscv/corev.md:836:0:████████(match_operand:QI 1 "move_operand"████████ " r,I,CV_mem_nopm,rJ,*r*J,*f,vp"))]
gcc/config/riscv/corev.md:847:0:████████(match_operand:HF 1 "move_operand"████████ " f,zfli,G,CV_mem_nopm,f,G,*r,*f,*G*r,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:858:0:████████(match_operand:HF 1 "move_operand"████████ " f,Gr,CV_mem_nopm,r,*r,*f"))]
gcc/config/riscv/corev.md:869:0:████████(zero_extend:GPR
gcc/config/riscv/corev.md:870:0:████████ (match_operand:HI 1 "nonimmediate_nonpostinc" " r,CV_mem_nopm")))]
gcc/config/riscv/corev.md:879:0:████████(ashift:GPR (match_dup 1) (match_dup 2)))
gcc/config/riscv/corev.md:881:0:████████(lshiftrt:GPR (match_dup 0) (match_dup 2)))]
gcc/config/riscv/corev.md:892:0:████████(zero_extend:SUPERQI
gcc/config/riscv/corev.md:893:0:████████ (match_operand:QI 1 "nonimmediate_nonpostinc" " r,CV_mem_nopm")))]
gcc/config/riscv/corev.md:904:0:████████(sign_extend:SUPERQI
gcc/config/riscv/corev.md:905:0:████████ (match_operand:SHORT 1 "nonimmediate_nonpostinc" " r,CV_mem_nopm")))]
gcc/config/riscv/corev.md:919:0:████████████████████████ - GET_MODE_BITSIZE (<SHORT:MODE>mode));
gcc/config/riscv/corev.md:927:0:████████(match_operand:DF 1 "move_operand"████████ " f,zfli,G,CV_mem_nopm,f,G,*zmvr,*zmvf,*r*G,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:938:0:████████(match_operand:DF 1 "move_operand"████████ " f,zfli,G,CV_mem_nopm,f,G,*r,*f,*r*G,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:949:0:████████(match_operand:DF 1 "move_operand"████████ " rG,CV_mem_nopm,rG"))]
gcc/config/riscv/corev.md:960:0:████████(match_operand:SF 1 "move_operand"████████ " f,zfli,G,CV_mem_nopm,f,G,*r,*f,*G*r,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:971:0:████████(match_operand:SF 1 "move_operand"████████ " Gr,CV_mem_nopm,r"))]
gcc/config/riscv/predicates.md:258:0:████████████████ && GET_MODE_SIZE (GET_MODE (op)).to_constant () <= 4")))
=== ERROR type #2: dot, space, space, end of comment (2 error(s)) ===
gcc/config/riscv/riscv.cc:1457:29: * or 12-bit immediate.█*/
gcc/config/riscv/riscv.cc:2630:9: * vaild.█*/
=== ERROR type #3: dot, space, space, new sentence (1 error(s)) ===
gcc/config/riscv/riscv.cc:2629:44:/* Check if post inc instructions are valid.█If not, make the address
=== ERROR type #4: lines should not exceed 80 characters (36 error(s)) ===
gcc/config/riscv/constraints.md:287:80: (and (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
gcc/config/riscv/corev.md:716:80: "TARGET_XCVMEM && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[1], 0), (lra_in_progress || reload_completed))"
gcc/config/riscv/corev.md:724:80: "TARGET_XCVMEM && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[1], 0), (lra_in_progress || reload_completed))"
gcc/config/riscv/corev.md:733:80: && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[1], 0), (lra_in_progress || reload_completed))
gcc/config/riscv/corev.md:743:80: "TARGET_XCVMEM && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[0], 0), (lra_in_progress || reload_completed))"
gcc/config/riscv/corev.md:752:80: && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[0], 0), (lra_in_progress || reload_completed))
gcc/config/riscv/corev.md:763:80: "TARGET_XCVMEM && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[1], 0), (lra_in_progress || reload_completed))"
gcc/config/riscv/corev.md:771:80: "TARGET_XCVMEM && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[1], 0), (lra_in_progress || reload_completed))"
gcc/config/riscv/corev.md:780:80: && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[1], 0), (lra_in_progress || reload_completed))
gcc/config/riscv/corev.md:790:80: "TARGET_XCVMEM && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[0], 0), (lra_in_progress || reload_completed))"
gcc/config/riscv/corev.md:799:80: && riscv_legitimate_xcvmem_address_p (<MODE>mode, XEXP (operands[0], 0), (lra_in_progress || reload_completed))
gcc/config/riscv/corev.md:811:80: [(set (match_operand:SI 0 "nonimmediate_nonpostinc" "=r,r,r,CV_mem_nopm, *f,*f,*r,*CV_mem_nopm,r")
gcc/config/riscv/corev.md:812:80: (match_operand:SI 1 "move_operand" " r,T,CV_mem_nopm,rJ,*r*J,*CV_mem_nopm,*f,*f,vp"))]
gcc/config/riscv/corev.md:824:80: [(set (match_operand:HI 0 "nonimmediate_nonpostinc" "=r,r,r,CV_mem_nopm, *f,*r,r")
gcc/config/riscv/corev.md:825:80: (match_operand:HI 1 "move_operand" " r,T,CV_mem_nopm,rJ,*r*J,*f,vp"))]
gcc/config/riscv/corev.md:835:80: [(set (match_operand:QI 0 "nonimmediate_nonpostinc" "=r,r,r,CV_mem_nopm, *f,*r,r")
gcc/config/riscv/corev.md:836:80: (match_operand:QI 1 "move_operand" " r,I,CV_mem_nopm,rJ,*r*J,*f,vp"))]
gcc/config/riscv/corev.md:846:80: [(set (match_operand:HF 0 "nonimmediate_nonpostinc" "=f, f,f,f,CV_mem_nopm,CV_mem_nopm,*f,*r, *r,*r,*CV_mem_nopm")
gcc/config/riscv/corev.md:847:80: (match_operand:HF 1 "move_operand" " f,zfli,G,CV_mem_nopm,f,G,*r,*f,*G*r,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:852:80: [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
gcc/config/riscv/corev.md:857:80: [(set (match_operand:HF 0 "nonimmediate_nonpostinc" "=f, r,r,CV_mem_nopm,*f,*r")
gcc/config/riscv/corev.md:858:80: (match_operand:HF 1 "move_operand" " f,Gr,CV_mem_nopm,r,*r,*f"))]
gcc/config/riscv/corev.md:905:80: (match_operand:SHORT 1 "nonimmediate_nonpostinc" " r,CV_mem_nopm")))]
gcc/config/riscv/corev.md:926:80: [(set (match_operand:DF 0 "nonimmediate_nonpostinc" "=f, f,f,f,CV_mem_nopm,CV_mem_nopm,*zmvf,*zmvr, *r,*r,*CV_mem_nopm")
gcc/config/riscv/corev.md:927:80: (match_operand:DF 1 "move_operand" " f,zfli,G,CV_mem_nopm,f,G,*zmvr,*zmvf,*r*G,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:932:80: [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
gcc/config/riscv/corev.md:937:80: [(set (match_operand:DF 0 "nonimmediate_nonpostinc" "=f, f,f,f,CV_mem_nopm,CV_mem_nopm,*f,*r, *r,*r,*CV_mem_nopm")
gcc/config/riscv/corev.md:938:80: (match_operand:DF 1 "move_operand" " f,zfli,G,CV_mem_nopm,f,G,*r,*f,*r*G,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:943:80: [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
gcc/config/riscv/corev.md:959:80: [(set (match_operand:SF 0 "nonimmediate_nonpostinc" "=f, f,f,f,CV_mem_nopm,CV_mem_nopm,*f,*r, *r,*r,*CV_mem_nopm")
gcc/config/riscv/corev.md:960:80: (match_operand:SF 1 "move_operand" " f,zfli,G,CV_mem_nopm,f,G,*r,*f,*G*r,*CV_mem_nopm,*r"))]
gcc/config/riscv/corev.md:965:80: [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
gcc/config/riscv/riscv.cc:1475:80: || (TARGET_XCVMEM && riscv_valid_base_register_p (info->offset, mode, strict_p))));
gcc/config/riscv/riscv.cc:2644:80: if (REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)) && riscv_classify_address (&addr, x, mode, strict_p))
gcc/config/riscv/riscv.cc:6004:80: if (REG_P (addr.offset)) fprintf (file, "%s", reg_names[REGNO (addr.offset)]);
gcc/config/riscv/riscv.cc:6025:80: if (REG_P (addr.offset)) fprintf (file, "%s", reg_names[REGNO (addr.offset)]);
=== ERROR type #5: there should be exactly one space between function name and parenthesis (2 error(s)) ===
gcc/config/riscv/corev.md:884:25: operands[2] = GEN_INT(GET_MODE_BITSIZE(<GPR:MODE>mode) - 16);
gcc/config/riscv/riscv.opt:428:4:Mask(XCVMEM) Var(riscv_xcv_subext)
ewlu
Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/7490501446
Patch information
Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=29556 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20240111144118.274895-2-mary.bennett@embecosm.com/ Patch id: 83903
Build Targets
multilib, please refer to the table below to see all the targets within that multilib.-marchstringrv32gc-ilp32d,rv64gc-lp64drv64gcv-lp64drv32gcv-ilp32d,rv64gcv-lp64dTarget Information
-marchstringgc_zba_zbb_zbc_zbsNotes
Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com