github-actions[bot] commented 4 months ago

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/7615176672

Patch information

Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=30055 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20240122171503.807456-2-mary.bennett@embecosm.com/ Patch id: 84567

Build Targets

Some targets are built as multilibs. If a build target ends with `multilib`, please refer to the table below to see all the targets within that multilib.	Target name	`-march` string
newlib-rv64gc-lp64d-multilib	`rv32gc-ilp32d`, `rv64gc-lp64d`
newlib-rv64gcv-lp64d-multilib	`rv64gcv-lp64d`
linux-rv64gcv-lp64d-multilib	`rv32gcv-ilp32d`, `rv64gcv-lp64d`

Target Information

Target Shorthand	`-march` string
Bitmanip	`gc_zba_zbb_zbc_zbs`

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

github-actions[bot] commented 4 months ago

Lint Status

The following issues have been found with 30055-RISCV_Support_COREV_XCVBITMAIP_extension-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: blocks of 8 spaces should be replaced with tabs (80 error(s)) ===
gcc/config/riscv/corev.def:49:112:RISCV_BUILTIN (cv_bitmanip_extract,     "cv_bitmanip_extract",     RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_USI_UHI,████████ cvbitmanip),
gcc/config/riscv/corev.def:50:113:RISCV_BUILTIN (cv_bitmanip_extractu,    "cv_bitmanip_extractu",    RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI,████████cvbitmanip),
gcc/config/riscv/corev.def:52:32:RISCV_BUILTIN (cv_bitmanip_bclr,████████"cv_bitmanip_bclr",████████RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI,████████cvbitmanip),
gcc/config/riscv/corev.def:53:32:RISCV_BUILTIN (cv_bitmanip_bset,████████"cv_bitmanip_bset",████████RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI,████████cvbitmanip),
gcc/config/riscv/corev.def:54:31:RISCV_BUILTIN (cv_bitmanip_ff1,████████ "cv_bitmanip_ff1",████████ RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,████████    cvbitmanip),
gcc/config/riscv/corev.def:55:31:RISCV_BUILTIN (cv_bitmanip_fl1,████████ "cv_bitmanip_fl1",████████ RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,████████    cvbitmanip),
gcc/config/riscv/corev.def:56:31:RISCV_BUILTIN (cv_bitmanip_clb,████████ "cv_bitmanip_clb",████████ RISCV_BUILTIN_DIRECT, RISCV_UQI_FTYPE_USI,████████    cvbitmanip),
gcc/config/riscv/corev.def:57:31:RISCV_BUILTIN (cv_bitmanip_cnt,████████ "cv_bitmanip_cnt",████████ RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,████████    cvbitmanip),
gcc/config/riscv/corev.def:58:31:RISCV_BUILTIN (cv_bitmanip_ror,████████ "cv_bitmanip_ror",████████ RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI,████████cvbitmanip),
gcc/config/riscv/corev.md:717:0:████████(sign_extract:SI
gcc/config/riscv/corev.md:718:0:████████  (match_operand:SI 1 "register_operand" "r,r")
gcc/config/riscv/corev.md:719:0:████████  (ashiftrt:SI
gcc/config/riscv/corev.md:720:0:████████    (match_operand:HI 2 "bit_extract_operand" "CV_bit_si10,r")
gcc/config/riscv/corev.md:721:0:████████    (const_int 5))
gcc/config/riscv/corev.md:722:0:████████  (plus:SI
gcc/config/riscv/corev.md:723:0:████████    (and:SI
gcc/config/riscv/corev.md:724:0:████████      (match_dup 2)
gcc/config/riscv/corev.md:725:0:████████      (const_int 31))
gcc/config/riscv/corev.md:726:0:████████    (const_int 1))))]
gcc/config/riscv/corev.md:737:0:████████(zero_extract:SI
gcc/config/riscv/corev.md:739:0:████████  (ashiftrt:SI
gcc/config/riscv/corev.md:740:0:████████    (match_operand:HI 2 "bit_extract_operand" "CV_bit_si10,r")
gcc/config/riscv/corev.md:741:0:████████    (const_int 5))
gcc/config/riscv/corev.md:742:0:████████  (plus:SI
gcc/config/riscv/corev.md:744:0:████████      (match_dup 2)
gcc/config/riscv/corev.md:745:0:████████      (const_int 31))
gcc/config/riscv/corev.md:746:0:████████    (const_int 1))))]
gcc/config/riscv/corev.md:758:0:████████  (and:SI
gcc/config/riscv/corev.md:759:0:████████    (match_operand:SI 3 "register_operand" "0,0")
gcc/config/riscv/corev.md:760:0:████████    (zero_extract:SI
gcc/config/riscv/corev.md:761:0:████████      (const_int 0)
gcc/config/riscv/corev.md:762:0:████████    (ashiftrt:SI
gcc/config/riscv/corev.md:763:0:████████      (match_operand:HI 2 "bit_extract_operand" "CV_bit_si10,r")
gcc/config/riscv/corev.md:764:0:████████      (const_int 5))
gcc/config/riscv/corev.md:765:0:████████    (plus:SI
gcc/config/riscv/corev.md:766:0:████████      (and:SI
gcc/config/riscv/corev.md:767:0:████████████████(match_dup 2)
gcc/config/riscv/corev.md:768:0:████████████████(const_int 31))
gcc/config/riscv/corev.md:769:0:████████      (const_int 1))))
gcc/config/riscv/corev.md:771:0:████████    (match_operand:SI 1 "register_operand" "r,r")
gcc/config/riscv/corev.md:772:0:████████    (ashiftrt:SI
gcc/config/riscv/corev.md:773:0:████████      (match_dup 2)
gcc/config/riscv/corev.md:774:0:████████      (const_int 5))
gcc/config/riscv/corev.md:775:0:████████    (plus:SI
gcc/config/riscv/corev.md:776:0:████████      (and:SI
gcc/config/riscv/corev.md:777:0:████████████████(match_dup 2)
gcc/config/riscv/corev.md:778:0:████████████████(const_int 31))
gcc/config/riscv/corev.md:779:0:████████      (const_int 1)))))]
gcc/config/riscv/corev.md:791:0:████████  (match_operand:SI 1 "register_operand" "r,r")
gcc/config/riscv/corev.md:794:0:████████  (ashiftrt:SI
gcc/config/riscv/corev.md:795:0:████████    (match_operand:HI 2 "bit_extract_operand" "CV_bit_si10,r")
gcc/config/riscv/corev.md:796:0:████████    (const_int 5))
gcc/config/riscv/corev.md:797:0:████████  (plus:SI
gcc/config/riscv/corev.md:798:0:████████    (and:SI
gcc/config/riscv/corev.md:799:0:████████      (match_dup 2)
gcc/config/riscv/corev.md:800:0:████████      (const_int 31))
gcc/config/riscv/corev.md:801:0:████████    (const_int 1)))))]
gcc/config/riscv/corev.md:812:0:████████(ior:SI
gcc/config/riscv/corev.md:813:0:████████  (match_operand:SI 1 "register_operand" "r,r")
gcc/config/riscv/corev.md:814:0:████████  (sign_extract:SI
gcc/config/riscv/corev.md:815:0:████████    (const_int -2)
gcc/config/riscv/corev.md:816:0:████████  (ashiftrt:SI
gcc/config/riscv/corev.md:817:0:████████    (match_operand:HI 2 "bit_extract_operand" "CV_bit_si10,r")
gcc/config/riscv/corev.md:818:0:████████    (const_int 5))
gcc/config/riscv/corev.md:819:0:████████  (plus:SI
gcc/config/riscv/corev.md:820:0:████████    (and:SI
gcc/config/riscv/corev.md:821:0:████████      (match_dup 2)
gcc/config/riscv/corev.md:822:0:████████      (const_int 31))
gcc/config/riscv/corev.md:823:0:████████    (const_int 1)))))]
gcc/config/riscv/corev.md:834:0:████████(ctz:SI (match_operand:SI 1 "register_operand" "r")))]
gcc/config/riscv/corev.md:854:0:████████(if_then_else (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))
gcc/config/riscv/corev.md:855:0:████████████████      (const_int 0)
gcc/config/riscv/corev.md:856:0:████████████████      (clrsb:QI (match_dup 1))))]
gcc/config/riscv/corev.md:865:0:████████(popcount:SI (match_operand:SI 1 "register_operand" "r")))]
gcc/config/riscv/corev.md:874:0:████████(rotatert:SI (match_operand:SI 1 "register_operand" "r")
gcc/config/riscv/corev.md:875:0:████████████████     (match_operand:SI 2 "register_operand" "r")))]
gcc/config/riscv/corev.md:884:0:████████(unspec:SI [(match_operand:SI 1 "register_operand" "r")
gcc/config/riscv/corev.md:885:0:████████████████    (match_operand:QI 2 "const_csr_operand" "K")
gcc/config/riscv/corev.md:886:0:████████████████    (match_operand:QI 3 "const_int2_operand" "D03")]
gcc/config/riscv/corev.md:887:0:████████ UNSPEC_CV_BITMANIP_BITREV))]

=== ERROR type #2: dot, space, space, new sentence (6 error(s)) ===
gcc/doc/extend.texi:24471:13:architecture.█For more information on CORE-V built-ins, please see
gcc/doc/extend.texi:24475:76:Generated assembler @code{cv.extract} if the uint16_t operand is a constant.█Generated assembler
gcc/doc/extend.texi:24480:77:Generated assembler @code{cv.extractu} if the uint16_t operand is a constant.█Generated assembler
gcc/doc/extend.texi:24485:75:Generated assembler @code{cv.insert} if the uint16_t operand is a constant.█Generated assembler
gcc/doc/extend.texi:24490:73:Generated assembler @code{cv.bclr} if the uint16_t operand is a constant.█Generated assembler
gcc/doc/extend.texi:24495:73:Generated assembler @code{cv.bset} if the uint16_t operand is a constant.█Generated assembler

=== ERROR type #3: lines should not exceed 80 characters (29 error(s)) ===
gcc/config/riscv/corev.def:49:80:RISCV_BUILTIN (cv_bitmanip_extract,     "cv_bitmanip_extract",     RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_USI_UHI,         cvbitmanip),
gcc/config/riscv/corev.def:50:80:RISCV_BUILTIN (cv_bitmanip_extractu,    "cv_bitmanip_extractu",    RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI,        cvbitmanip),
gcc/config/riscv/corev.def:51:80:RISCV_BUILTIN (cv_bitmanip_insert,      "cv_bitmanip_insert",      RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI_USI,    cvbitmanip),
gcc/config/riscv/corev.def:52:80:RISCV_BUILTIN (cv_bitmanip_bclr,        "cv_bitmanip_bclr",        RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI,        cvbitmanip),
gcc/config/riscv/corev.def:53:80:RISCV_BUILTIN (cv_bitmanip_bset,        "cv_bitmanip_bset",        RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI,        cvbitmanip),
gcc/config/riscv/corev.def:54:80:RISCV_BUILTIN (cv_bitmanip_ff1,         "cv_bitmanip_ff1",         RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,            cvbitmanip),
gcc/config/riscv/corev.def:55:80:RISCV_BUILTIN (cv_bitmanip_fl1,         "cv_bitmanip_fl1",         RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,            cvbitmanip),
gcc/config/riscv/corev.def:56:80:RISCV_BUILTIN (cv_bitmanip_clb,         "cv_bitmanip_clb",         RISCV_BUILTIN_DIRECT, RISCV_UQI_FTYPE_USI,            cvbitmanip),
gcc/config/riscv/corev.def:57:80:RISCV_BUILTIN (cv_bitmanip_cnt,         "cv_bitmanip_cnt",         RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,            cvbitmanip),
gcc/config/riscv/corev.def:58:80:RISCV_BUILTIN (cv_bitmanip_ror,         "cv_bitmanip_ror",         RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI,        cvbitmanip),
gcc/config/riscv/corev.def:59:80:RISCV_BUILTIN (cv_bitmanip_bitrev,      "cv_bitmanip_bitrev",      RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI_UQI,    cvbitmanip),
gcc/config/riscv/corev.md:854:80:        (if_then_else (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))
gcc/doc/extend.texi:24472:80:@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#pulp-bit-manipulation-builtins-for-32-bit-cores}
gcc/doc/extend.texi:24474:80:@deftypefn {Built-in Function} {int32_t} __builtin_riscv_cv_bitmanip_extract (uint32_t, uint16_t)
gcc/doc/extend.texi:24475:80:Generated assembler @code{cv.extract} if the uint16_t operand is a constant. Generated assembler
gcc/doc/extend.texi:24479:80:@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_bitmanip_extractu (uint32_t, uint16_t)
gcc/doc/extend.texi:24480:80:Generated assembler @code{cv.extractu} if the uint16_t operand is a constant. Generated assembler
gcc/doc/extend.texi:24484:80:@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_bitmanip_insert (uint32_t, uint16_t, uint32_t)
gcc/doc/extend.texi:24485:80:Generated assembler @code{cv.insert} if the uint16_t operand is a constant. Generated assembler
gcc/doc/extend.texi:24489:80:@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_bitmanip_bclr (uint32_t, uint16_t)
gcc/doc/extend.texi:24490:80:Generated assembler @code{cv.bclr} if the uint16_t operand is a constant. Generated assembler
gcc/doc/extend.texi:24494:80:@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_bitmanip_bset (uint32_t, uint16_t)
gcc/doc/extend.texi:24495:80:Generated assembler @code{cv.bset} if the uint16_t operand is a constant. Generated assembler
gcc/doc/extend.texi:24499:80:@deftypefn {Built-in Function} {uint8_t} __builtin_riscv_cv_bitmanip_ff1 (uint32_t)
gcc/doc/extend.texi:24503:80:@deftypefn {Built-in Function} {uint8_t} __builtin_riscv_cv_bitmanip_fl1 (uint32_t)
gcc/doc/extend.texi:24507:80:@deftypefn {Built-in Function} {uint8_t} __builtin_riscv_cv_bitmanip_clb (uint32_t)
gcc/doc/extend.texi:24511:80:@deftypefn {Built-in Function} {uint8_t} __builtin_riscv_cv_bitmanip_cnt (uint32_t)
gcc/doc/extend.texi:24515:80:@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_bitmanip_ror (uint32_t, uint32_t)
gcc/doc/extend.texi:24519:80:@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_bitmanip_bitrev (uint32_t, uint8_t, uint8_t)

=== ERROR type #4: there should be exactly one space between function name and parenthesis (1 error(s)) ===
gcc/config/riscv/riscv.opt:428:4:Mask(XCVBITMANIP) Var(riscv_xcv_subext)

Additional information

github-actions[bot] commented 4 months ago

Apply Status

Target	Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5	Applied
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/41caf6b0d603408a829b37f7f7fb09d64d814d48	Applied

Notes

Patch applied successfully

Additional information

github-actions[bot] commented 4 months ago

Build GCC Status

Target	Status
linux-rv64gc_zba_zbb_zbc_zbs-lp64d-non-multilib	Success
linux-rv32gc_zba_zbb_zbc_zbs-ilp32d-non-multilib	Success
newlib-rv64gc-lp64d-multilib	Success
linux-rv64gcv-lp64d-multilib	Success
newlib-rv64gcv-lp64d-multilib	Success

Notes

Patch(es) were applied to the hash https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5. If this patch commit depends on or conflicts with a recently committed patch, then these results may be outdated.

Additional information

github-actions[bot] commented 4 months ago

Testsuite Status

Summary

New Failures	gcc	g++	gfortran	Previous Hash
linux: rv32gcv ilp32d medlow multilib	4/3	0/0	0/0	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5

Resolved Failures	gcc	g++	gfortran	Previous Hash

Unresolved Failures	gcc	g++	gfortran	Previous Hash
linux: rv32 Bitmanip ilp32d medlow	34/14	15/8	13/3	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5
linux: rv32gcv ilp32d medlow multilib	75/38	32/16	16/4	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5
linux: rv64 Bitmanip lp64d medlow	27/12	10/4	13/3	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5
linux: rv64gcv lp64d medlow multilib	50/31	14/5	13/3	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5
newlib: rv32gc ilp32d medlow multilib	64/19	89/16	0/0	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5
newlib: rv64gc lp64d medlow multilib	49/15	60/10	0/0	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5
newlib: rv64gcv lp64d medlow multilib	69/32	64/11	0/0	https://github.com/gcc-mirror/gcc/commit/a57439d61937925cec48df6166b2a805ae7054d5

New Failures Across All Affected Targets (1 targets / 7 total targets)

FAIL: gcc.dg/vect/tsvc/vect-tsvc-s1351.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/tsvc/vect-tsvc-s1351.c execution test
FAIL: gcc.dg/vect/tsvc/vect-tsvc-s352.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/tsvc/vect-tsvc-s422.c -flto -ffat-lto-objects execution test

Additional information

ewlu commented 4 months ago

/pass_test

ewlu / gcc-precommit-ci

Patch Status 30055-RISCV_Support_COREV_XCVBITMAIP_extension-1 #1230

Precommit CI Run information

Patch information

Build Targets

Target Information

Notes

Lint Status

Apply Status

Notes

Build GCC Status

Notes

Testsuite Status

Summary

New Failures Across All Affected Targets (1 targets / 7 total targets)