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Patch Status 31115-RISCV_Revert_the_convert_from_vmvsx_to_vmvvi-1 #1333

Closed github-actions[bot] closed 3 months ago

github-actions[bot] commented 8 months ago

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/7968555575

Patch information

Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=31115 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/or8r3fpy9d.fsf@lxoliva.fsfla.org/ Patch id: 86012

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib. Target name -march string
newlib-rv64gc-lp64d-multilib rv32gc-ilp32d, rv64gc-lp64d
newlib-rv64gcv-lp64d-multilib rv64gcv-lp64d
linux-rv64gcv-lp64d-multilib rv32gcv-ilp32d, rv64gcv-lp64d

Target Information

Target Shorthand -march string
Bitmanip gc_zba_zbb_zbc_zbs

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

github-actions[bot] commented 8 months ago

Lint Status

The following issues have been found with 31115-RISCV_Revert_the_convert_from_vmvsx_to_vmvvi-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: blocks of 8 spaces should be replaced with tabs (10 error(s)) ===
gcc/config/riscv/vector.md:1353:45:  [(set (match_operand:V 0 "register_operand"████████████████████████  "=vr,    vr")
gcc/config/riscv/vector.md:1356:0:████████[(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1,   Wb1")
gcc/config/riscv/vector.md:1357:0:████████ (match_operand 4 "vector_length_operand"████████████████████████  " rK,    rK")
gcc/config/riscv/vector.md:1358:0:████████ (match_operand 5 "const_int_operand"████████████████████████      "  i,     i")
gcc/config/riscv/vector.md:1359:0:████████ (match_operand 6 "const_int_operand"████████████████████████      "  i,     i")
gcc/config/riscv/vector.md:1360:0:████████ (match_operand 7 "const_int_operand"████████████████████████      "  i,     i")
gcc/config/riscv/vector.md:1361:0:████████ (reg:SI VL_REGNUM)
gcc/config/riscv/vector.md:1362:0:████████ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
gcc/config/riscv/vector.md:1363:49:      (match_operand:V 3 "vector_const_0_operand"████████████████      "Wc0,   Wc0")
gcc/config/riscv/vector.md:1364:47:      (match_operand:V 2 "vector_merge_operand"████████████████████████" vu,     0")))]

=== ERROR type #2: dot, space, space, end of comment (1 error(s)) ===
gcc/config/riscv/vector.md:1231:47:            vl = 0 or 1; + vlse.v (TU) in RV32 system  */

=== ERROR type #3: lines should not exceed 80 characters (8 error(s)) ===
gcc/config/riscv/vector.md:1353:80:  [(set (match_operand:V 0 "register_operand"                          "=vr,    vr")
gcc/config/riscv/vector.md:1356:80:        [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1,   Wb1")
gcc/config/riscv/vector.md:1357:80:         (match_operand 4 "vector_length_operand"                          " rK,    rK")
gcc/config/riscv/vector.md:1358:80:         (match_operand 5 "const_int_operand"                              "  i,     i")
gcc/config/riscv/vector.md:1359:80:         (match_operand 6 "const_int_operand"                              "  i,     i")
gcc/config/riscv/vector.md:1360:80:         (match_operand 7 "const_int_operand"                              "  i,     i")
gcc/config/riscv/vector.md:1363:80:      (match_operand:V 3 "vector_const_0_operand"                      "Wc0,   Wc0")
gcc/config/riscv/vector.md:1364:80:      (match_operand:V 2 "vector_merge_operand"                        " vu,     0")))]

Additional information

github-actions[bot] commented 8 months ago

Apply Status

Target Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/eb17bdc211ab12fd53b0a6bc926ef7ecbce40c72 Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/524902784662306f11fb37ccb1956af9bb3d9784 Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 RISC-V: Revert the convert from vmv.s.x to vmv.v.i
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---
 gcc/config/riscv/predicates.md                     |    4 ++
 gcc/config/riscv/vector.md                         |   43 ++++++++++++++------
 .../gcc.target/riscv/rvv/base/scalar_move-5.c      |   20 ++++++++-
 .../gcc.target/riscv/rvv/base/scalar_move-6.c      |   22 ++++++++--
 4 files changed, 70 insertions(+), 19 deletions(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 8654dbc594354..1707c80cba256 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -276,6 +276,10 @@ (define_predicate "reg_or_int_operand"
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "const_int_operand")))

+(define_predicate "vector_const_0_operand"
+  (and (match_code "const_vector")
+       (match_test "satisfies_constraint_Wc0 (op)")))
+
 (define_predicate "vector_move_operand"
   (ior (match_operand 0 "nonimmediate_operand")
        (and (match_code "const_vector")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index db3a972832aea..fb0caab8da360 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1217,23 +1217,24 @@ (define_expand "@pred_broadcast<mode>"
      (match_operand:V 2 "vector_merge_operand")))]
   "TARGET_VECTOR"
 {
-  /* Handle vmv.s.x instruction which has memory scalar.  */
-  if (satisfies_constraint_Wdm (operands[3]) || riscv_vector::simm5_p (operands[3])
-      || rtx_equal_p (operands[3], CONST0_RTX (<VEL>mode)))
+  /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar.  */
+  if (satisfies_constraint_Wdm (operands[3]))
     {
       if (satisfies_constraint_Wb1 (operands[1]))
-        {
-          // Case 1: vmv.s.x (TA) ==> vlse.v (TA)
-          if (satisfies_constraint_vu (operands[2]))
-            operands[1] = CONSTM1_RTX (<VM>mode);
-          else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
-            {
-         // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
+   {
+     /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA)  */
+     if (satisfies_constraint_vu (operands[2]))
+       operands[1] = CONSTM1_RTX (<VM>mode);
+     else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
+       {
+         /* Case 2: vmv.s.x (TU, x == memory) ==>
+              vl = 0 or 1; + vlse.v (TU) in RV32 system  */
          operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
          operands[1] = CONSTM1_RTX (<VM>mode);
        }
-          else
-            operands[3] = force_reg (<VEL>mode, operands[3]);
+     else
+       /* Case 3: load x (memory) to register.  */
+       operands[3] = force_reg (<VEL>mode, operands[3]);
    }
     }
   else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
@@ -1348,6 +1349,24 @@ (define_insn "*pred_broadcast<mode>_extended_scalar"
   [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
    (set_attr "mode" "<MODE>")])

+(define_insn "*pred_broadcast<mode>_zero"
+  [(set (match_operand:V 0 "register_operand"                          "=vr,    vr")
+    (if_then_else:V
+      (unspec:<VM>
+        [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1,   Wb1")
+         (match_operand 4 "vector_length_operand"                          " rK,    rK")
+         (match_operand 5 "const_int_operand"                              "  i,     i")
+         (match_operand 6 "const_int_operand"                              "  i,     i")
+         (match_operand 7 "const_int_operand"                              "  i,     i")
+         (reg:SI VL_REGNUM)
+         (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+      (match_operand:V 3 "vector_const_0_operand"                      "Wc0,   Wc0")
+      (match_operand:V 2 "vector_merge_operand"                        " vu,     0")))]
+  "TARGET_VECTOR"
+  "vmv.s.x\t%0,zero"
+  [(set_attr "type" "vimovxv,vimovxv")
+   (set_attr "mode" "<MODE>")])
+
 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated Strided loads/stores
 ;; -------------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c
index db6800c89781b..2e897a4896fec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c
@@ -121,7 +121,7 @@ void foo8 (void *base, void *out, size_t vl, double x)
 /*
 ** foo9:
 ** ...
-** vmv.v.i\tv[0-9]+,\s*-15
+** vmv.s.x\tv[0-9]+,\s*[a-x0-9]+
 ** ...
 ** ret
 */
@@ -150,7 +150,7 @@ void foo10 (void *base, void *out, size_t vl)
 /*
 ** foo11:
 ** ...
-** vmv.v.i\tv[0-9]+,\s*0
+** vmv.s.x\tv[0-9]+,\s*zero
 ** ...
 ** ret
 */
@@ -164,7 +164,7 @@ void foo11 (void *base, void *out, size_t vl)
 /*
 ** foo12:
 ** ...
-** vfmv.s.f\tv[0-9]+,\s*[a-x0-9]+
+** vmv.s.x\tv[0-9]+,\s*zero
 ** ...
 ** ret
 */
@@ -174,3 +174,17 @@ void foo12 (void *base, void *out, size_t vl)
     vfloat64m2_t v = __riscv_vfmv_s_f_f64m2_tu (merge, 0, vl);
     *(vfloat64m2_t*)out = v;
 }
+
+/*
+** foo13:
+** ...
+** vfmv.s.f\tv[0-9]+,\s*[a-x0-9]+
+** ...
+** ret
+*/
+void foo13 (void *base, void *out, size_t vl)
+{
+    vfloat64m2_t merge = *(vfloat64m2_t*) (base + 200);
+    vfloat64m2_t v = __riscv_vfmv_s_f_f64m2_tu (merge, 0.2, vl);
+    *(vfloat64m2_t*)out = v;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c
index f27f85cdb5866..326cfd8e2ff4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c
@@ -119,7 +119,7 @@ void foo8 (void *base, void *out, size_t vl, double x)
 /*
 ** foo9:
 ** ...
-** vmv.v.i\tv[0-9]+,\s*-15
+** vmv.s.x\tv[0-9]+,\s*[a-x0-9]+
 ** ...
 ** ret
 */
@@ -133,7 +133,7 @@ void foo9 (void *base, void *out, size_t vl)
 /*
 ** foo10:
 ** ...
-** vmv.v.i\tv[0-9]+,\s*-15
+** vmv.s.x\tv[0-9]+,\s*[a-x0-9]+
 ** ...
 */
 void foo10 (void *base, void *out, size_t vl)
@@ -147,7 +147,7 @@ void foo10 (void *base, void *out, size_t vl)
 /*
 ** foo11:
 ** ...
-** vmv.v.i\tv[0-9]+,\s*0
+** vmv.s.x\tv[0-9]+,\s*zero
 ** ...
 ** ret
 */
@@ -161,7 +161,7 @@ void foo11 (void *base, void *out, size_t vl)
 /*
 ** foo12:
 ** ...
-** vmv.v.i\tv[0-9]+,\s*0
+** vmv.s.x\tv[0-9]+,\s*zero
 ** ...
 ** ret
 */
@@ -172,6 +172,20 @@ void foo12 (void *base, void *out, size_t vl)
     *(vfloat64m2_t*)out = v;
 }

+/*
+** foo12_1:
+** ...
+** vfmv.s.f\tv[0-9]+,\s*[a-x0-9]+
+** ...
+** ret
+*/
+void foo12_1 (void *base, void *out, size_t vl)
+{
+    vfloat64m2_t merge = *(vfloat64m2_t*) (base + 200);
+    vfloat64m2_t v = __riscv_vfmv_s_f_f64m2_tu (merge, 0.2, vl);
+    *(vfloat64m2_t*)out = v;
+}
+
 /*
 ** foo13:
 ** ...

Additional information